wehub-resource-sync
131 lines
5.2 KiB
Plaintext
131 lines
5.2 KiB
Plaintext
// Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "paddle/phi/kernels/nms_kernel.h"
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#include "paddle/phi/backends/gpu/cuda/cuda_graph_with_memory_pool.h"
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#include "paddle/phi/backends/gpu/gpu_context.h"
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#include "paddle/phi/backends/gpu/gpu_primitives.h"
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#include "paddle/phi/common/memory_utils.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/kernels/funcs/math_function.h"
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static const int64_t threadsPerBlock = sizeof(int64_t) * 8;
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namespace phi {
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template <typename T>
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static __global__ void NMS(const T* boxes_data,
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float threshold,
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int64_t num_boxes,
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uint64_t* masks) {
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auto raw_start = blockIdx.y;
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auto col_start = blockIdx.x;
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if (raw_start > col_start) return;
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const int raw_last_storage =
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min(num_boxes - raw_start * threadsPerBlock, threadsPerBlock);
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const int col_last_storage =
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min(num_boxes - col_start * threadsPerBlock, threadsPerBlock);
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if (threadIdx.x < raw_last_storage) {
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uint64_t mask = 0;
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auto current_box_idx = raw_start * threadsPerBlock + threadIdx.x;
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const T* current_box = boxes_data + current_box_idx * 4;
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for (int i = 0; i < col_last_storage; ++i) {
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const T* target_box = boxes_data + (col_start * threadsPerBlock + i) * 4;
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if (CalculateIoU<T>(current_box, target_box, threshold)) {
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mask |= 1ULL << i;
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}
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}
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const int blocks_per_line = CeilDivide(num_boxes, threadsPerBlock);
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masks[current_box_idx * blocks_per_line + col_start] = mask;
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}
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}
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template <typename T, typename Context>
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void NMSKernel(const Context& dev_ctx,
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const DenseTensor& boxes,
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float threshold,
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DenseTensor* output) {
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PADDLE_ENFORCE_EQ(
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boxes.dims().size(),
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2,
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common::errors::InvalidArgument("The shape [%s] of boxes must be (N, 4).",
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boxes.dims()));
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PADDLE_ENFORCE_EQ(
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boxes.dims()[1],
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4,
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common::errors::InvalidArgument("The shape [%s] of boxes must be (N, 4).",
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boxes.dims()));
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const int64_t num_boxes = boxes.dims()[0];
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const auto blocks_per_line = CeilDivide(num_boxes, threadsPerBlock);
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dim3 block(threadsPerBlock);
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dim3 grid(blocks_per_line, blocks_per_line);
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auto mask_data =
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memory_utils::Alloc(dev_ctx.GetPlace(),
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num_boxes * blocks_per_line * sizeof(uint64_t),
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Stream(reinterpret_cast<StreamId>(dev_ctx.stream())));
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uint64_t* mask_dev = reinterpret_cast<uint64_t*>(mask_data->ptr());
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NMS<T><<<grid, block, 0, dev_ctx.stream()>>>(
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boxes.data<T>(), threshold, num_boxes, mask_dev);
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PADDLE_ENFORCE_EQ(
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backends::gpu::IsCUDAGraphCapturing(),
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false,
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common::errors::InvalidArgument(
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"NMSKernel does not support CUDA Graph capture: async D2H copy to "
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"local vector 'mask_host' will bake the destination address into the "
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"graph; on replay the vector is re-created at a different address, "
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"causing a dangling-pointer write."));
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std::vector<uint64_t> mask_host(num_boxes * blocks_per_line);
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memory_utils::Copy(CPUPlace(),
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mask_host.data(),
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dev_ctx.GetPlace(),
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mask_dev,
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num_boxes * blocks_per_line * sizeof(uint64_t),
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dev_ctx.stream());
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std::vector<int64_t> remv(blocks_per_line);
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std::vector<int64_t> keep_boxes_idxs(num_boxes);
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int64_t* output_host = keep_boxes_idxs.data();
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int64_t last_box_num = 0;
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for (int64_t i = 0; i < num_boxes; ++i) {
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auto remv_element_id = i / threadsPerBlock;
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auto remv_bit_id = i % threadsPerBlock;
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if (!(remv[remv_element_id] & 1ULL << remv_bit_id)) {
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output_host[last_box_num++] = i;
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uint64_t* current_mask = mask_host.data() + i * blocks_per_line;
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for (auto j = remv_element_id; j < blocks_per_line; ++j) {
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remv[j] |= current_mask[j];
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}
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}
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}
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output->Resize({last_box_num});
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auto* output_data = dev_ctx.template Alloc<int64_t>(output);
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const int64_t* stable_output =
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backends::gpu::RestoreHostMemIfCapturingCUDAGraph(output_host,
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last_box_num);
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memory_utils::Copy(dev_ctx.GetPlace(),
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output_data,
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CPUPlace(),
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stable_output,
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sizeof(int64_t) * last_box_num,
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dev_ctx.stream());
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}
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} // namespace phi
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PD_REGISTER_KERNEL(nms, GPU, ALL_LAYOUT, phi::NMSKernel, float, double) {
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kernel->OutputAt(0).SetDataType(phi::DataType::INT64);
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}
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