wehub-resource-sync
103 lines
3.6 KiB
Plaintext
103 lines
3.6 KiB
Plaintext
// Copyright (c) 2024 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "paddle/phi/kernels/affine_channel_kernel.h"
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#include "paddle/phi/backends/gpu/gpu_context.h"
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#include "paddle/phi/backends/gpu/gpu_primitives.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/kernels/funcs/cub.h"
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namespace phi {
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template <typename T, DataLayout layout, bool HasBias>
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__global__ static inline void KeAffineChannelCUDA(const T* x,
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const T* scale,
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const T* bias,
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const int C,
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const int64_t HxW,
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const int64_t num,
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T* y) {
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int64_t gid =
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static_cast<int64_t>(blockIdx.x) * static_cast<int64_t>(blockDim.x) +
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static_cast<int64_t>(threadIdx.x);
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int stride = blockDim.x * gridDim.x;
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for (int64_t i = gid; i < num; i += stride) {
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const int c = layout == DataLayout::NCHW ? i / HxW % C : i % C;
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if (HasBias) {
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y[i] = scale[c] * x[i] + bias[c];
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} else {
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y[i] = scale[c] * x[i];
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}
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}
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}
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template <typename T, typename Context>
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void AffineChannelCUDAKernel(const Context& dev_ctx,
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const DenseTensor& x_in,
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const DenseTensor& scale_in,
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const DenseTensor& bias_in,
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const std::string& data_layout,
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DenseTensor* out) {
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auto* x = &x_in;
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auto* scale = &scale_in;
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auto* bias = &bias_in;
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auto* y = out;
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dev_ctx.template Alloc<T>(y);
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const DataLayout layout = StringToDataLayout(data_layout);
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auto dims = x->dims();
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const int64_t num = x->numel();
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int64_t N = dims[0];
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int64_t C = layout == DataLayout::NCHW ? dims[1] : dims[dims.size() - 1];
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int64_t HxW = num / N / C;
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const T* x_d = x->data<T>();
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const T* scale_d = scale->data<T>();
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const T* bias_d = bias->data<T>();
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T* y_d = y->data<T>();
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#ifdef PADDLE_WITH_HIP
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int block = 256;
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#else
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int block = 1024;
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#endif // PADDLE_WITH_HIP
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int grid = (num + block - 1) / block;
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int max_threads = dev_ctx.GetMaxPhysicalThreadCount();
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grid = std::min(std::max(max_threads / block, 1), grid);
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// NOTE(large-tensor): KeAffineChannelCUDA function signature uses int for C
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// parameter
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PADDLE_ENFORCE_LE_INT_MAX(C, "C");
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if (layout == DataLayout::NCHW) {
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KeAffineChannelCUDA<T, DataLayout::NCHW, true>
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<<<grid, block, 0, dev_ctx.stream()>>>(
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x_d, scale_d, bias_d, static_cast<int>(C), HxW, num, y_d);
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} else {
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KeAffineChannelCUDA<T, DataLayout::NHWC, true>
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<<<grid, block, 0, dev_ctx.stream()>>>(
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x_d, scale_d, bias_d, static_cast<int>(C), HxW, num, y_d);
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}
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}
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} // namespace phi
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PD_REGISTER_KERNEL(affine_channel,
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GPU,
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ALL_LAYOUT,
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phi::AffineChannelCUDAKernel,
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float,
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double) {}
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