// Copyright (c) 2024 PaddlePaddle Authors. All Rights Reserved.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

#include "paddle/phi/kernels/affine_channel_kernel.h"
#include "paddle/phi/backends/gpu/gpu_context.h"
#include "paddle/phi/backends/gpu/gpu_primitives.h"
#include "paddle/phi/core/kernel_registry.h"
#include "paddle/phi/kernels/funcs/cub.h"

namespace phi {

template <typename T, DataLayout layout, bool HasBias>
__global__ static inline void KeAffineChannelCUDA(const T* x,
                                                  const T* scale,
                                                  const T* bias,
                                                  const int C,
                                                  const int64_t HxW,
                                                  const int64_t num,
                                                  T* y) {
  int64_t gid =
      static_cast<int64_t>(blockIdx.x) * static_cast<int64_t>(blockDim.x) +
      static_cast<int64_t>(threadIdx.x);
  int stride = blockDim.x * gridDim.x;
  for (int64_t i = gid; i < num; i += stride) {
    const int c = layout == DataLayout::NCHW ? i / HxW % C : i % C;
    if (HasBias) {
      y[i] = scale[c] * x[i] + bias[c];
    } else {
      y[i] = scale[c] * x[i];
    }
  }
}

template <typename T, typename Context>
void AffineChannelCUDAKernel(const Context& dev_ctx,
                             const DenseTensor& x_in,
                             const DenseTensor& scale_in,
                             const DenseTensor& bias_in,
                             const std::string& data_layout,
                             DenseTensor* out) {
  auto* x = &x_in;
  auto* scale = &scale_in;
  auto* bias = &bias_in;

  auto* y = out;
  dev_ctx.template Alloc<T>(y);

  const DataLayout layout = StringToDataLayout(data_layout);

  auto dims = x->dims();
  const int64_t num = x->numel();
  int64_t N = dims[0];
  int64_t C = layout == DataLayout::NCHW ? dims[1] : dims[dims.size() - 1];
  int64_t HxW = num / N / C;

  const T* x_d = x->data<T>();
  const T* scale_d = scale->data<T>();
  const T* bias_d = bias->data<T>();
  T* y_d = y->data<T>();

#ifdef PADDLE_WITH_HIP
  int block = 256;
#else
  int block = 1024;
#endif  // PADDLE_WITH_HIP
  int grid = (num + block - 1) / block;

  int max_threads = dev_ctx.GetMaxPhysicalThreadCount();
  grid = std::min(std::max(max_threads / block, 1), grid);

  // NOTE(large-tensor): KeAffineChannelCUDA function signature uses int for C
  // parameter
  PADDLE_ENFORCE_LE_INT_MAX(C, "C");
  if (layout == DataLayout::NCHW) {
    KeAffineChannelCUDA<T, DataLayout::NCHW, true>
        <<<grid, block, 0, dev_ctx.stream()>>>(
            x_d, scale_d, bias_d, static_cast<int>(C), HxW, num, y_d);
  } else {
    KeAffineChannelCUDA<T, DataLayout::NHWC, true>
        <<<grid, block, 0, dev_ctx.stream()>>>(
            x_d, scale_d, bias_d, static_cast<int>(C), HxW, num, y_d);
  }
}
}  // namespace phi

PD_REGISTER_KERNEL(affine_channel,
                   GPU,
                   ALL_LAYOUT,
                   phi::AffineChannelCUDAKernel,
                   float,
                   double) {}