wehub-resource-sync
323 lines
14 KiB
Plaintext
323 lines
14 KiB
Plaintext
/* Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/phi/kernels/sparse/conv_kernel.h"
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#include "paddle/phi/backends/gpu/gpu_context.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/core/tensor_meta.h"
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#include "paddle/phi/core/visit_type.h"
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#include "paddle/phi/kernels/cast_kernel.h"
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#include "paddle/phi/kernels/funcs/blas/blas.h"
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#include "paddle/phi/kernels/funcs/scatter.cu.h"
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#include "paddle/phi/kernels/funcs/sparse/scatter.cu.h"
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#include "paddle/phi/kernels/sparse/gpu/conv.cu.h"
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#include "paddle/phi/kernels/sparse/gpu/conv_host_buffer.h"
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#include "glog/logging.h"
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namespace phi {
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namespace sparse {
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#define GATHER_GEMM_SCATTER(arch, input_type, x_nnz, kernel) \
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({ \
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const input_type* kernel_ptr = kernel.data<input_type>(); \
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const input_type* x_nnz_ptr = x_nnz.data<input_type>(); \
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for (int i = 0; i < kernel_size; i++) { \
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if (h_counter_ptr[i] <= 0) { \
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continue; \
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} \
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const int M = h_counter_ptr[i]; \
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const int K = in_channels; \
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const int N = out_channels; \
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const input_type* tmp_kernel_ptr = kernel_ptr + i * K * N; \
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const IntT* gather_indices = rulebook_ptr + h_offsets_ptr[i]; \
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const IntT* scatter_indices = \
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rulebook_ptr + rulebook_len + h_offsets_ptr[i]; \
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const size_t key = autotune::GenKey(M / features_num_range, N, K); \
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GatherGemmScatterDriver<arch, false, false>( \
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dev_ctx, \
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key, \
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x_nnz_ptr, \
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tmp_kernel_ptr, \
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out_values_ptr, \
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out_values_ptr, \
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M, \
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N, \
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K, \
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gather_indices, \
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static_cast<const IntT*>(nullptr), \
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scatter_indices, \
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static_cast<T>(1.0), \
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static_cast<T>(1.0), \
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nullptr); \
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} \
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})
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template <typename T, typename IntT>
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void Conv3dCooGPUKernel(const GPUContext& dev_ctx,
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const SparseCooTensor& x,
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const DenseTensor& kernel,
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const std::vector<int>& paddings,
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const std::vector<int>& dilations,
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const std::vector<int>& strides,
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const int groups,
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const bool subm,
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const std::string& key,
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SparseCooTensor* out,
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DenseTensor* rulebook,
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DenseTensor* counter) {
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// update padding and dilation
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// Currently, only support x.layout is NDHWC, groups = 1
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// if x.layout != NDHWC then transpose(x), transpose(weight)
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const auto& x_dims = x.dims();
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const auto& kernel_dims = kernel.dims();
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const bool is2D = x_dims.size() == 4 ? true : false;
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int kernel_size = is2D ? kernel_dims[0] * kernel_dims[1]
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: kernel_dims[0] * kernel_dims[1] * kernel_dims[2];
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int rank = is2D ? 4 : 5;
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std::vector<int> out_dims_vec(rank, 1);
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DDim out_dims = make_ddim(out_dims_vec);
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std::vector<int> kernel_sizes(kernel_dims.size());
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for (int i = 0; i < kernel_dims.size(); i++) {
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kernel_sizes[i] = kernel_dims[i];
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}
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std::vector<int> subm_paddings(paddings), subm_strides(strides);
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if (subm) {
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// the out shape of subm_conv is same as input shape
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// reset the padding=kernel_size/2 and strides=1
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funcs::sparse::ResetSubmKernelSizeAndStrides(
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kernel.dims(), &subm_paddings, &subm_strides);
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}
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funcs::sparse::GetOutShape(
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x_dims, kernel_sizes, subm_paddings, dilations, subm_strides, &out_dims);
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const int in_channels = is2D ? kernel_dims[2] : kernel_dims[3];
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const int out_channels = is2D ? kernel_dims[3] : kernel_dims[4];
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int* h_counter_ptr{nullptr};
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int* h_offsets_ptr{nullptr};
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phi::sparse::ConvHostBuffer& conv_host_buffer =
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phi::sparse::ConvHostBuffer::getInstance();
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DenseTensor h_counter, h_offsets;
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if (conv_host_buffer.using_buffer()) {
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int* h_buffer_ptr = conv_host_buffer.get_host_buffer();
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h_counter_ptr = h_buffer_ptr;
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h_offsets_ptr = h_buffer_ptr + kernel_size;
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} else {
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h_counter.Resize({kernel_size});
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h_offsets.Resize({kernel_size + 1});
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h_counter_ptr = dev_ctx.template HostAlloc<int>(&h_counter);
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h_offsets_ptr = dev_ctx.template HostAlloc<int>(&h_offsets);
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}
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// Second algorithm:
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// https://pdfs.semanticscholar.org/5125/a16039cabc6320c908a4764f32596e018ad3.pdf
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// 1. product rulebook
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DenseTensor counter_per_kernel = Empty<int>(dev_ctx, {kernel_size});
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DenseTensor offsets_per_kernel = Empty<int>(dev_ctx, {kernel_size});
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DenseTensor out_index = Empty<int>(dev_ctx, {1});
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DenseTensor unique_value = Empty<int>(dev_ctx, {1});
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if (is2D) {
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VLOG(6) << "call SubmConv2D or Conv2D " << subm << " and the key is "
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<< key;
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} else {
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VLOG(6) << "call SubmConv3D or Conv3D " << subm << " and the key is "
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<< key;
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}
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int rulebook_len = 0;
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const IntT* rulebook_ptr = nullptr;
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bool need_product_rulebook = true;
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if (subm && !key.empty()) {
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rulebook_ptr =
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funcs::sparse::PrepareSubm<T, IntT, GPUContext>(dev_ctx,
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x,
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key,
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out_dims,
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out,
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h_counter_ptr,
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h_offsets_ptr,
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&rulebook_len,
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&need_product_rulebook);
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}
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if (need_product_rulebook) {
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DenseTensor tmp_rulebook;
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rulebook_len = ProductRuleBook<T, GPUContext, IntT>(dev_ctx,
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x,
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kernel_sizes,
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subm_paddings,
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dilations,
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subm_strides,
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out_dims,
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subm,
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&tmp_rulebook,
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&counter_per_kernel,
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&offsets_per_kernel,
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&out_index,
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&unique_value,
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out,
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h_counter_ptr,
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h_offsets_ptr);
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rulebook_ptr = tmp_rulebook.data<IntT>();
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DenseTensor h_counter_tensor;
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h_counter_tensor.Resize({kernel_size});
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int* h_counter_tensor_ptr =
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dev_ctx.template HostAlloc<int>(&h_counter_tensor);
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for (int i = 0; i < kernel_size; ++i) {
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h_counter_tensor_ptr[i] = h_counter_ptr[i];
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}
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funcs::sparse::SaveToTable(dev_ctx,
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x,
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key,
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tmp_rulebook,
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h_counter_tensor,
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out,
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rulebook,
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counter);
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}
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if (subm) {
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auto config = backends::gpu::GetGpuLaunchConfig1D(dev_ctx, rulebook_len, 1);
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unique_value.ResizeAndAllocate(
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{static_cast<int>(out->nnz() * kernel_size)});
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out_index.ResizeAndAllocate({static_cast<int>(rulebook_len)});
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int* out_index_ptr = out_index.data<int>();
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int* unique_value_ptr = unique_value.data<int>();
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backends::gpu::GpuMemsetAsync(
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out_index_ptr, 0, sizeof(int) * rulebook_len, dev_ctx.stream());
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GroupIndices<<<config.block_per_grid,
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config.thread_per_block,
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0,
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dev_ctx.stream()>>>(rulebook_len,
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kernel_size,
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rulebook_ptr + rulebook_len,
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out_index_ptr,
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unique_value_ptr);
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}
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// 2. gather
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DenseTensor in_features = Empty<T>(dev_ctx, {rulebook_len, in_channels});
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DenseTensor out_features = Empty<T>(dev_ctx, {rulebook_len, out_channels});
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T* in_features_ptr = in_features.data<T>();
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T* out_features_ptr = out_features.data<T>();
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funcs::SetConstant<GPUContext, T> set_zero;
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set_zero(dev_ctx, &out_features, static_cast<T>(0.0f));
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Gather<T, IntT>(dev_ctx,
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x.values().data<T>(),
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rulebook_ptr,
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rulebook_len,
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in_channels,
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in_features_ptr);
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// 3. call gemm for every werght
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auto blas = funcs::GetBlas<GPUContext, T>(dev_ctx);
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auto* out_values = out->mutable_values();
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T* out_values_ptr = out_values->data<T>();
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set_zero(dev_ctx, out_values, static_cast<T>(0.0f));
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const T* kernel_ptr = kernel.data<T>();
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for (int i = 0; i < kernel_size; i++) {
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if (h_counter_ptr[i] <= 0) {
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continue;
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}
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// call gemm: (n, in_channels) * (in_channels, out_channels)
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const int M = h_counter_ptr[i];
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const int K = in_channels;
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const int N = out_channels;
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T* tmp_in_ptr = in_features_ptr + h_offsets_ptr[i] * in_channels;
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const T* tmp_kernel_ptr = kernel_ptr + i * K * N;
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T* tmp_out_ptr = out_features_ptr + h_offsets_ptr[i] * out_channels;
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blas.GEMM(CblasNoTrans,
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CblasNoTrans,
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M,
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N,
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K,
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static_cast<T>(1),
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tmp_in_ptr,
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tmp_kernel_ptr,
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static_cast<T>(0),
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tmp_out_ptr);
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}
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// 4. scatter
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funcs::sparse::ScatterV2<T>(dev_ctx,
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out_features_ptr,
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out_index.data<int>(),
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unique_value.data<int>(),
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out->nnz(),
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kernel_size,
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out_channels,
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1,
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out_values_ptr);
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}
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/**
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* x: the input SparseCooTensor, shape is (N, D, H, W, C)
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* kernel: the weight data, shape is (D, H, W, C, OC)
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* out: the output SparseCooTensor, shape is (N, D, H, W, OC)
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* rulebook: return rulebook if key is not valid else return nullptr
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* counter: return counter if key is not valid else return nullptr
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**/
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template <typename T, typename Context>
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void Conv3dCooKernel(const Context& dev_ctx,
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const SparseCooTensor& x,
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const DenseTensor& kernel,
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const std::vector<int>& paddings,
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const std::vector<int>& dilations,
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const std::vector<int>& strides,
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const int groups,
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const bool subm,
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const std::string& key,
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SparseCooTensor* out,
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DenseTensor* rulebook,
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DenseTensor* counter) {
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PD_VISIT_BASE_INTEGRAL_TYPES(x.indices().dtype(), "Conv3dCooGPUKernel", ([&] {
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Conv3dCooGPUKernel<T, data_t>(dev_ctx,
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x,
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kernel,
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paddings,
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dilations,
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strides,
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groups,
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subm,
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key,
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out,
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rulebook,
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counter);
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}));
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}
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} // namespace sparse
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} // namespace phi
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PD_REGISTER_KERNEL(conv3d_coo,
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GPU,
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ALL_LAYOUT,
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phi::sparse::Conv3dCooKernel,
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float,
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double,
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phi::float16) {
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kernel->InputAt(0).SetDataLayout(phi::DataLayout::SPARSE_COO);
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kernel->OutputAt(0).SetDataType(phi::DataType::UNDEFINED);
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kernel->OutputAt(1).SetDataType(phi::DataType::INT32);
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kernel->OutputAt(2).SetDataType(phi::DataType::INT32);
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}
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