wehub-resource-sync
71 lines
3.9 KiB
Markdown
71 lines
3.9 KiB
Markdown
# ESP Hardware Abstraction Layer for USB Peripheral(s)
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> [!NOTE]
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> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
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## Overview
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The `esp_hal_usb` component provides a **Hardware Abstraction Layer** for USB controllers and PHYs across all ESP-IDF supported targets. USB (Universal Serial Bus) enables communication between the ESP device and USB hosts or devices, supporting various USB speeds and transfer types for data exchange.
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## Architecture
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The USB HAL is structured in two main sub-layers:
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1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control USB peripherals (e.g., initialization, endpoint configuration, transfer management, PHY control).
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2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
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## Supported USB Controllers and PHYs
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This HAL supports various USB controller and PHY types depending on the ESP chip:
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- **USB-DWC (DesignWare USB Controller)**: The main USB OTG controller supporting USB Host and Device modes
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- **USB Serial JTAG**: A special USB peripheral that combines USB CDC-ACM functionality with JTAG debugging capabilities
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- **USB WRAP**: A wrapper/peripheral controller that provides additional USB functionality and GPIO matrix integration
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- **USB PHY Types**:
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- **FSLS (Full Speed/Low Speed) Internal PHY**: Built-in PHY supporting USB Full Speed and Low Speed operation
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- **FSLS External PHY**: Support for external FSLS PHY via GPIO matrix
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- **UTMI PHY**: UTMI+ compliant PHY interface for High Speed USB support
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## Features
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- USB controller initialization and configuration
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- Endpoint management (IN/OUT endpoints)
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- Transfer type support (Control, Bulk, Interrupt, Isochronous)
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- USB speed detection and configuration (High Speed, Full Speed, Low Speed)
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- FIFO configuration and management
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- PHY initialization and control (FSLS and UTMI)
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- GPIO matrix signal routing for USB PHY interfaces
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- OTG (On-The-Go) signal handling
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- Interrupt management and event handling
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- Multi-controller support (on chips with multiple USB controllers)
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## Usage
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The HAL functions primarily serve ESP-IDF USB drivers, primarily the [USB Host stack](https://components.espressif.com/components/espressif/usb).
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## Dependencies
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- `soc`: Provides chip-specific register definitions
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- `hal`: Core hardware abstraction utilities and macros
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## Hardware configuration
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The USB-DWC2 peripheral has many internal configuration parameters. The configuration is saved `GHWCFGx` registers. Configuration parameters which are often checked in run-time, are cached in USB-HAL context variable `usb_dwc_hal_context_t::constant_config` to limit access to the registers and offload system bus.
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### Selected configuration parameters across ESP SoCs
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| | S2, S3, H4 & P4-OTG1.1 | P4-OTG2.0, version < 3 | P4-OTG2.0, version >= 3 |
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|--------------------|------------------------|-------------------------|-------------------------|
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| HS PHY interface | None | UTMI+ 16bit | UTMI+ 16bit |
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| Single point | Yes | No (SPLIT supported) | No (SPLIT supported) |
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| Number of channels | 8 | 16 | 16 |
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| FIFO depth | 256 lines (1024 bytes) | 1024 lines (4096 bytes) | 1024 lines (4096 bytes) |
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| Perio queue depth | 8 | 4 | 16 |
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| NPerio queue depth | 4 | 4 | 8 |
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| Transfer cnt width | 16bits (max 65,535) | 16bits (max 65,535) | 19bits (max 524,287) |
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| Packet cnt width | 7bits (max 127) | 7bits (max 127) | 10bits (max 1,023) |
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