wehub-resource-sync
123 lines
4.1 KiB
Python
123 lines
4.1 KiB
Python
# Licensed to the Apache Software Foundation (ASF) under one
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# or more contributor license agreements. See the NOTICE file
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# distributed with this work for additional information
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# regarding copyright ownership. The ASF licenses this file
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# to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance
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# with the License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing,
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# software distributed under the License is distributed on an
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# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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# KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations
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# under the License.
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import re
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import pytest
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import tvm
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import tvm.contrib.hexagon as hexagon
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import tvm.testing
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from tvm.script import ir as I
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from tvm.script import tirx as T
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from tvm.testing import env
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@pytest.fixture(autouse=True)
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def register_linker():
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original_linker = hexagon.hexagon_link()
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# Register a phony linker, so that we can test codegen without a Hexagon toolchain.
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hexagon.register_linker(lambda: "/bin/true")
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yield None
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# Restore registration.
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hexagon.register_linker(original_linker)
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@pytest.mark.skipif(not env.has_hexagon(), reason="need hexagon")
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def test_basic():
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target = tvm.target.Target("qcom/hexagon-v66")
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@I.ir_module(s_tir=True)
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class Module:
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@T.prim_func(s_tir=True)
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def main(
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C: T.Buffer((128,), "uint8"),
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A: T.Buffer((128,), "uint8"),
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A_1: T.Buffer((128,), "uint8"),
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):
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T.func_attr({"tirx.noalias": True})
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for i in range(128):
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with T.sblock("C"):
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v_i = T.axis.spatial(128, i)
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T.reads(A[v_i], A_1[v_i])
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T.writes(C[v_i])
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C[v_i] = A[v_i] + A_1[v_i]
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hexm = tvm.compile(Module, target=tvm.target.Target(target, target))
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asm = hexm.inspect_source("s")
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vadds = re.findall(r"v[0-9]+.b = vadd\(v[0-9]+.b,v[0-9]+.b\)", asm)
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assert vadds # Check that it's non-empty
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@pytest.mark.skipif(not env.has_hexagon(), reason="need hexagon")
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def test_llvm_target_features():
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target = tvm.target.Target("qcom/hexagon-v66")
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@I.ir_module(s_tir=True)
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class Module:
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@T.prim_func(s_tir=True)
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def add_one(C: T.Buffer((128,), "int32"), A: T.Buffer((128,), "uint8")):
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T.func_attr({"tirx.noalias": True})
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for i in range(128):
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with T.sblock("C"):
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v_i = T.axis.spatial(128, i)
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T.reads(A[v_i])
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T.writes(C[v_i])
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C[v_i] = T.Cast("int32", A[v_i]) + 1
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m = tvm.compile(Module, target=tvm.target.Target(target, target))
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llvm_ir = m.inspect_source("ll")
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# Make sure we find +hvx-length128b in "attributes".
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fs = re.findall(r"attributes.*\+hvx-length128b", llvm_ir)
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assert fs # Check that it's non-empty
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@pytest.mark.skipif(not env.has_hexagon(), reason="need hexagon")
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def test_llvm_options():
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target = tvm.target.Target(
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{
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"kind": "hexagon",
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"mtriple": "hexagon",
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"mcpu": "hexagonv66",
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"mattr": ["+hvxv66", "+hvx-length128b"],
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"num-cores": 4,
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"vtcm-capacity": 262144,
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"llvm-options": ["-hexagon-noopt"],
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}
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)
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@I.ir_module(s_tir=True)
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class Module:
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@T.prim_func(s_tir=True)
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def main(compute: T.Buffer((10,), "int32")):
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T.func_attr({"tirx.noalias": True})
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for _ in range(10):
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with T.sblock("compute"):
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v__ = T.axis.spatial(10, _)
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T.reads()
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T.writes(compute[v__])
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compute[v__] = 0
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# Check that BuildHexagon hasn't crashed because of target attribute
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# type mismatch.
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tvm.compile(Module, target=tvm.target.Target(target, target))
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assert re.search("-hexagon-noopt", str(target))
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if __name__ == "__main__":
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tvm.testing.main()
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