wehub-resource-sync
81 lines
2.8 KiB
Python
81 lines
2.8 KiB
Python
# Licensed to the Apache Software Foundation (ASF) under one
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# or more contributor license agreements. See the NOTICE file
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# distributed with this work for additional information
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# regarding copyright ownership. The ASF licenses this file
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# to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance
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# with the License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing,
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# software distributed under the License is distributed on an
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# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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# KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations
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# under the License.
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"""The Relax CPU backend compilation pipeline and other passes."""
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import tvm
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from tvm import relax
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def library_dispatch_passes(target: tvm.target.Target): # pylint: disable=unused-argument
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"""The default library dispatch passes for CPU backend."""
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return [
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relax.backend.DispatchSampling(),
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relax.backend.DispatchSortScan(),
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]
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def legalize_passes(target: tvm.target.Target): # pylint: disable=unused-argument
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"""The default legalization passes for CPU backend."""
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return [
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tvm.relax.transform.LegalizeOps(),
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tvm.relax.transform.AnnotateTIROpPattern(),
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tvm.relax.transform.FoldConstant(),
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tvm.relax.transform.FuseOps(),
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tvm.relax.transform.FuseTIR(),
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]
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def dataflow_lower_passes(target: tvm.target.Target): # pylint: disable=unused-argument
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"""The default dataflow lowering passes for CPU backend."""
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return [
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relax.transform.RewriteDataflowReshape(),
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relax.transform.ToNonDataflow(),
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relax.transform.RemovePurityChecking(),
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relax.transform.CallTIRRewrite(),
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]
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def finalize_passes(target: tvm.target.Target): # pylint: disable=unused-argument
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"""The default finalization passes for CPU backend."""
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return [
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relax.transform.StaticPlanBlockMemory(),
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relax.transform.LowerAllocTensor(),
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relax.transform.KillAfterLastUse(),
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relax.transform.LowerRuntimeBuiltin(),
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relax.transform.ComputePrimValue(),
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relax.transform.VMShapeLower(),
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relax.transform.AttachGlobalSymbol(),
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]
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def get_default_pipeline(target: tvm.target.Target):
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"""Return the default compilation pipeline for CPU."""
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@tvm.transform.module_pass(opt_level=0)
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def _pipeline(mod: tvm.ir.IRModule, _ctx: tvm.transform.PassContext):
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with target:
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seq = tvm.transform.Sequential(
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library_dispatch_passes(target)
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+ legalize_passes(target)
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+ dataflow_lower_passes(target)
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+ finalize_passes(target)
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)
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mod = seq(mod)
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return mod
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return _pipeline
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