101 lines
3.3 KiB
Plaintext
101 lines
3.3 KiB
Plaintext
/*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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namespace vllm {
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namespace cuda_async {
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__device__ __forceinline__ void cp_async_shared_global_16_cg(
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void* smem_ptr, const void* glob_ptr) {
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#if defined(USE_ROCM)
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*reinterpret_cast<int4*>(smem_ptr) = *reinterpret_cast<const int4*>(glob_ptr);
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#elif defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800
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uint32_t smem = static_cast<uint32_t>(__cvta_generic_to_shared(smem_ptr));
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asm volatile("cp.async.cg.shared.global [%0], [%1], 16;\n"
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:
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: "r"(smem), "l"(glob_ptr));
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#elif defined(__CUDA_ARCH__)
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*reinterpret_cast<int4*>(smem_ptr) = *reinterpret_cast<const int4*>(glob_ptr);
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#else
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(void)smem_ptr;
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(void)glob_ptr;
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#endif
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}
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__device__ __forceinline__ void cp_async_shared_global_ca(void* smem_ptr,
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const void* glob_ptr,
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int size_bytes) {
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#if defined(USE_ROCM)
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if (size_bytes == 4) {
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*reinterpret_cast<uint32_t*>(smem_ptr) =
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*reinterpret_cast<const uint32_t*>(glob_ptr);
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} else if (size_bytes == 8) {
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*reinterpret_cast<uint64_t*>(smem_ptr) =
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*reinterpret_cast<const uint64_t*>(glob_ptr);
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} else {
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*reinterpret_cast<int4*>(smem_ptr) =
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*reinterpret_cast<const int4*>(glob_ptr);
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}
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#elif defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800
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uint32_t smem = static_cast<uint32_t>(__cvta_generic_to_shared(smem_ptr));
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if (size_bytes == 4) {
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asm volatile("cp.async.ca.shared.global [%0], [%1], 4;\n"
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:
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: "r"(smem), "l"(glob_ptr));
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} else if (size_bytes == 8) {
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asm volatile("cp.async.ca.shared.global [%0], [%1], 8;\n"
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:
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: "r"(smem), "l"(glob_ptr));
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} else {
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asm volatile("cp.async.ca.shared.global [%0], [%1], 16;\n"
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:
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: "r"(smem), "l"(glob_ptr));
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}
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#elif defined(__CUDA_ARCH__)
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if (size_bytes == 4) {
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*reinterpret_cast<uint32_t*>(smem_ptr) =
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*reinterpret_cast<const uint32_t*>(glob_ptr);
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} else if (size_bytes == 8) {
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*reinterpret_cast<uint64_t*>(smem_ptr) =
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*reinterpret_cast<const uint64_t*>(glob_ptr);
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} else {
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*reinterpret_cast<int4*>(smem_ptr) =
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*reinterpret_cast<const int4*>(glob_ptr);
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}
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#else
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(void)smem_ptr;
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(void)glob_ptr;
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(void)size_bytes;
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#endif
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}
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__device__ __forceinline__ void cp_async_commit_group() {
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#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 && !defined(USE_ROCM)
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asm volatile("cp.async.commit_group;\n" ::);
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#endif
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}
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template <int n>
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__device__ __forceinline__ void cp_async_wait_group() {
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#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 800 && !defined(USE_ROCM)
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asm volatile("cp.async.wait_group %0;\n" : : "n"(n));
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#endif
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}
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} // namespace cuda_async
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} // namespace vllm
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