wehub-resource-sync
78 lines
2.4 KiB
Systemverilog
78 lines
2.4 KiB
Systemverilog
// sample.sv - SystemVerilog fixture for parser tests
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`timescale 1ns / 1ps
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// File-level package import
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import utils_pkg::*;
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// Interface declaration
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interface BusIf #(parameter int WIDTH = 8);
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logic [WIDTH-1:0] data;
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logic valid;
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logic ready;
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modport master(output data, valid, input ready);
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modport slave(input data, valid, output ready);
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endinterface
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// Submodule to be instantiated by FIFOController
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module Adder #(parameter int WIDTH = 8) (input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] sum);
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assign sum = a + b;
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endmodule
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// Main module with tasks, functions, always blocks, and module instantiation
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// Parameters on one line to avoid grammar parse errors
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module FIFOController #(parameter int DEPTH = 16, parameter int WIDTH = 8) (
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input logic clk,
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input logic rst_n,
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input logic [WIDTH-1:0] data_in,
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input logic wr_en,
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input logic rd_en,
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output logic [WIDTH-1:0] data_out,
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output logic full,
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output logic empty
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);
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// Intra-module package import
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import arith_pkg::counter_t;
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logic [WIDTH-1:0] mem [0:DEPTH-1];
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logic [$clog2(DEPTH):0] wr_ptr, rd_ptr, count;
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// Module instantiation - creates CALLS edge from FIFOController to Adder
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Adder #(.WIDTH(WIDTH)) ptr_adder (.a(wr_ptr[WIDTH-1:0]), .b(rd_ptr[WIDTH-1:0]), .sum());
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// Task declaration
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task automatic do_write(input logic [WIDTH-1:0] din);
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mem[wr_ptr] <= din;
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wr_ptr <= wr_ptr + 1;
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count <= count + 1;
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endtask
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// Function declaration
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function automatic logic is_full();
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return (count >= DEPTH);
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endfunction
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// Always block (sequential logic) - flattened to avoid nested begin/end
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// grammar limitation: if(x) begin..end inside else begin..end causes parse errors
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wr_ptr <= 0;
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rd_ptr <= 0;
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count <= 0;
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end
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if (rst_n && wr_en && !full) do_write(data_in);
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if (rst_n && rd_en && !empty) begin
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data_out <= mem[rd_ptr];
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rd_ptr <= rd_ptr + 1;
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count <= count - 1;
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end
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end
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// Always block (combinational logic)
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always_comb begin
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full = is_full();
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empty = (count == 0);
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end
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endmodule
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