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147 lines
4.5 KiB
Python
147 lines
4.5 KiB
Python
# SPDX-License-Identifier: Apache-2.0
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# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
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# Adapted from https://github.com/vllm-project/vllm/blob/4868b542c9dfd166662eecc4bb8be3a36a3feaa2/vllm/cute_utils/cvt.py
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from cutlass import Constexpr, Float32, Uint32, cute
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from cutlass._mlir import ir
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from cutlass._mlir.dialects import llvm, vector
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from cutlass.cutlass_dsl import T, dsl_user_op
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@dsl_user_op
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def fp32x2_to_bf16x2(a: Float32, b: Float32, *, loc=None, ip=None) -> Uint32:
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out = llvm.inline_asm(
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T.i32(),
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[a.ir_value(loc=loc, ip=ip), b.ir_value(loc=loc, ip=ip)],
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"cvt.rn.bf16x2.f32 $0, $2, $1;",
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"=r,f,f",
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has_side_effects=False,
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is_align_stack=False,
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)
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return Uint32(out)
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@dsl_user_op
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def bf16x2_to_fp32x2(data, *, loc=None, ip=None) -> tuple[Float32, Float32]:
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if isinstance(data, Uint32):
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out = llvm.inline_asm(
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llvm.StructType.get_literal([T.f32(), T.f32()]),
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[data.ir_value(loc=loc, ip=ip)],
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"shl.b32 $0, $2, 16;\n\tand.b32 $1, $2, 0xFFFF0000;",
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"=f,=f,r",
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has_side_effects=False,
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is_align_stack=False,
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loc=loc,
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ip=ip,
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)
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return (
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Float32(llvm.extractvalue(T.f32(), out, [0], loc=loc, ip=ip)),
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Float32(llvm.extractvalue(T.f32(), out, [1], loc=loc, ip=ip)),
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)
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elif isinstance(data, (cute.Tensor, cute.TensorSSA)):
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# NOTE: the output is always 1D
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size = cute.size(data.shape)
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out = cute.make_rmem_tensor(size * 2, Float32)
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for i in range(size):
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out[i * 2], out[i * 2 + 1] = bf16x2_to_fp32x2(data[i])
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return out
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else:
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raise ValueError(f"Unsupported type {type(data)}")
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@dsl_user_op
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def fp8x4_to_bf16x4(x: Uint32, *, loc=None, ip=None) -> cute.TensorSSA:
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# there is only fp8->fp16 conversion, hence we need to go
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# round trip through fp16.
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out = llvm.inline_asm(
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llvm.StructType.get_literal([T.i32()] * 2),
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[x.ir_value(loc=loc, ip=ip)],
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"{\n\t"
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".reg .b16 x0, x1;\n\t"
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".reg .b16 t00, t01, t10, t11;\n\t"
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"mov.b32 {x0, x1}, $2;\n\t"
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"cvt.rn.f16x2.e4m3x2 $0, x0;\n\t"
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"cvt.rn.f16x2.e4m3x2 $1, x1;\n\t"
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"mov.b32 {t00, t01}, $0;\n\t"
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"mov.b32 {t10, t11}, $1;\n\t"
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"cvt.rn.bf16.f16 t00, t00;\n\t"
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"cvt.rn.bf16.f16 t01, t01;\n\t"
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"cvt.rn.bf16.f16 t10, t10;\n\t"
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"cvt.rn.bf16.f16 t11, t11;\n\t"
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"mov.b32 $0, {t00, t01};\n\t"
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"mov.b32 $1, {t10, t11};\n\t"
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"}\n",
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"=r,=r,r",
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has_side_effects=False,
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is_align_stack=False,
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)
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vec = vector.from_elements(
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ir.VectorType.get([2], T.i32(), loc=loc),
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[llvm.extractvalue(T.i32(), out, [i], loc=loc, ip=ip) for i in range(2)],
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loc=loc,
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ip=ip,
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)
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return cute.TensorSSA(vec, 2, Uint32)
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@dsl_user_op
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def fp32x4_to_fp8x4(
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a0: Float32,
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a1: Float32,
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a2: Float32,
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a3: Float32,
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*,
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loc=None,
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ip=None,
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) -> Uint32:
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# Pack four FP32 values into one b32 of four e4m3 bytes, byte order
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# {a0, a1, a2, a3} from low to high address.
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out = llvm.inline_asm(
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T.i32(),
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[
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a0.ir_value(loc=loc, ip=ip),
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a1.ir_value(loc=loc, ip=ip),
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a2.ir_value(loc=loc, ip=ip),
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a3.ir_value(loc=loc, ip=ip),
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],
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"{\n\t"
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".reg .b16 t0, t1;\n\t"
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"cvt.rn.satfinite.e4m3x2.f32 t0, $2, $1;\n\t"
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"cvt.rn.satfinite.e4m3x2.f32 t1, $4, $3;\n\t"
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"mov.b32 $0, {t0, t1};\n\t"
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"}\n",
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"=r,f,f,f,f",
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has_side_effects=False,
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is_align_stack=False,
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)
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return Uint32(out)
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@dsl_user_op
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def fp32x8_to_fp4x8(
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vals: cute.Tensor,
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offset: Constexpr[int],
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*,
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loc=None,
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ip=None,
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) -> Uint32:
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# Pack eight scaled FP32 values into four E2M1x2 bytes, returned as one b32.
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assert vals.element_type is Float32
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out = llvm.inline_asm(
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T.i32(),
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[vals[offset + i].ir_value(loc=loc, ip=ip) for i in range(8)],
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"{\n\t"
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".reg .b8 x0, x1, x2, x3;\n\t"
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"cvt.rn.satfinite.e2m1x2.f32 x0, $2, $1;\n\t"
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"cvt.rn.satfinite.e2m1x2.f32 x1, $4, $3;\n\t"
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"cvt.rn.satfinite.e2m1x2.f32 x2, $6, $5;\n\t"
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"cvt.rn.satfinite.e2m1x2.f32 x3, $8, $7;\n\t"
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"mov.b32 $0, {x0, x1, x2, x3};\n\t"
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"}\n",
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"=r,f,f,f,f,f,f,f,f",
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has_side_effects=False,
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is_align_stack=False,
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)
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return Uint32(out)
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