wehub-resource-sync
429 lines
15 KiB
Plaintext
429 lines
15 KiB
Plaintext
// Copyright (c) 2025 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "paddle/phi/kernels/median_kernel.h"
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#include <thrust/device_ptr.h>
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#include <thrust/execution_policy.h>
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#include <thrust/extrema.h>
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#include <thrust/functional.h>
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#include <thrust/reduce.h>
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#include "paddle/phi/backends/gpu/gpu_context.h"
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#include "paddle/phi/backends/gpu/gpu_launch_config.h"
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#include "paddle/phi/backends/gpu/gpu_primitives.h"
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#include "paddle/phi/common/memory_utils.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/kernels/full_kernel.h"
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#include "paddle/phi/kernels/funcs/nanmedian_utils.h"
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#include "paddle/phi/kernels/top_k_kernel.h"
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#if defined(__NVCC__) || defined(__HIPCC__)
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#include "paddle/phi/backends/gpu/gpu_device_function.h"
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#include "paddle/phi/kernels/primitive/kernel_primitives.h"
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#endif
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constexpr int64_t ELEMWISE_MAX_BLOCK_DIM = 1024;
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namespace phi {
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template <typename T>
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__global__ void KernelNanCounts(const T* input,
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const int64_t numel,
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const int64_t pre_dim,
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const int64_t stride,
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int64_t* nan_counts,
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int64_t* nan_indices) {
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int bx = blockIdx.x;
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int tx = threadIdx.x;
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int64_t total1 = 0;
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int64_t total2 = 0;
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for (int64_t j = bx; j < pre_dim; j += gridDim.x) {
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int64_t num = 0;
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int64_t i = tx;
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while (i < stride) {
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int64_t offset = i + j * stride;
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T x = input[offset];
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if (isnan(static_cast<float>(x))) {
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if (i < nan_indices[j]) nan_indices[j] = offset;
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num += 1;
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}
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i += blockDim.x;
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}
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int len = stride > blockDim.x ? blockDim.x : stride;
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num = backends::gpu::reduceSum(num, tx, len);
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if (tx == 0) {
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nan_counts[j] = num;
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}
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}
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}
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template <typename T>
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__global__ void CalcMedianMeanKernel(const T* sort_out_ptr,
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const int64_t* sort_indices_ptr,
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int64_t* nan_counts,
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int64_t* nan_indice,
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T nan_val,
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int64_t* median_val,
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T* output,
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T div_factor,
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const bool is_odd,
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const int64_t pre_dim,
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const int64_t stride) {
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int64_t begin = static_cast<int64_t>(blockIdx.x) * blockDim.x + threadIdx.x;
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int64_t step = static_cast<int64_t>(blockDim.x) * gridDim.x;
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for (int64_t index = begin; index < pre_dim; index += step) {
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if (nan_counts[index] > 0) {
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output[index] = nan_val;
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median_val[index] = nan_indice[index];
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continue;
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}
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int64_t pos = static_cast<int64_t>((index + 1) * stride) - 1;
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if (is_odd) {
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median_val[index * 2] = sort_indices_ptr[pos];
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median_val[index * 2 + 1] = sort_indices_ptr[pos];
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output[index] = sort_out_ptr[pos];
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} else {
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T median_val_left = pos > 0 ? sort_out_ptr[pos - 1] : sort_out_ptr[pos];
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T median_val_right = sort_out_ptr[pos];
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median_val[index * 2] =
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pos > 0 ? sort_indices_ptr[pos - 1] : sort_indices_ptr[pos];
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median_val[index * 2 + 1] = sort_indices_ptr[pos];
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output[index] = (median_val_left + median_val_right) / div_factor;
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}
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}
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}
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template <typename T>
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__global__ void CalcMedianMinKernel(const T* sort_out_ptr,
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const int64_t* sort_indices_ptr,
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int64_t* nan_counts,
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int64_t* nan_indice,
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T nan_val,
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int64_t* median_val,
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T* output,
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T div_factor,
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const bool is_odd,
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const int64_t pre_dim,
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const int64_t stride) {
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int64_t begin = static_cast<int64_t>(blockIdx.x) * blockDim.x + threadIdx.x;
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int64_t step = static_cast<int64_t>(blockDim.x) * gridDim.x;
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for (int64_t index = begin; index < pre_dim; index += step) {
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if (nan_counts[index] > 0) {
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output[index] = nan_val;
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median_val[index] = nan_indice[index];
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continue;
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}
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int64_t pos = static_cast<int64_t>((index + 1) * stride) - 1;
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if (is_odd) {
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median_val[index] = sort_indices_ptr[pos];
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output[index] = sort_out_ptr[pos];
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} else {
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T median_val_left = pos > 0 ? sort_out_ptr[pos - 1] : sort_out_ptr[pos];
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median_val[index] =
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pos > 0 ? sort_indices_ptr[pos - 1] : sort_indices_ptr[pos];
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output[index] = median_val_left;
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}
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}
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}
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template <typename T>
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__global__ void CalcNanmedianMeanKernel(const T* sort_out_ptr,
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const int64_t* sort_indices_ptr,
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int64_t* nan_counts,
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int64_t* median_val,
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T* output,
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const bool is_odd,
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const int64_t pre_dim,
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const int64_t max_valid_num,
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const int64_t stride,
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const T div_factor,
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const T nan_val) {
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int64_t begin = static_cast<int64_t>(blockIdx.x) * blockDim.x + threadIdx.x;
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int64_t step = static_cast<int64_t>(blockDim.x) * gridDim.x;
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for (int64_t index = begin; index < pre_dim; index += step) {
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int64_t pos = static_cast<int64_t>(index * max_valid_num);
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int64_t nan_cnt = nan_counts[index];
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if (nan_cnt == stride) {
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median_val[index * 2] = -1;
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median_val[index * 2 + 1] = -1;
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output[index] = nan_val;
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} else {
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int64_t nan_k =
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nan_cnt > 0 ? static_cast<int64_t>(stride - nan_cnt) : max_valid_num;
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int64_t row_pos = static_cast<int64_t>(nan_k >> 1);
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pos += row_pos;
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if (nan_k & 1) {
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median_val[index * 2] = sort_indices_ptr[pos];
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median_val[index * 2 + 1] = sort_indices_ptr[pos];
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output[index] = sort_out_ptr[pos];
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} else {
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T median_val_left = pos > 0 ? sort_out_ptr[pos - 1] : sort_out_ptr[pos];
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T median_val_right = sort_out_ptr[pos];
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median_val[index * 2] =
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pos > 0 ? sort_indices_ptr[pos - 1] : sort_indices_ptr[pos];
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median_val[index * 2 + 1] = sort_indices_ptr[pos];
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output[index] = (median_val_left + median_val_right) / div_factor;
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}
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}
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}
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}
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template <typename T>
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__global__ void CalcNanmedianMinKernel(const T* sort_out_ptr,
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const int64_t* sort_indices_ptr,
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int64_t* nan_counts,
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int64_t* median_val,
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T* output,
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const bool is_odd,
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const int64_t pre_dim,
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const int64_t max_valid_num,
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const int64_t stride,
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const T div_factor,
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const T nan_val) {
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int64_t begin = static_cast<int64_t>(blockIdx.x) * blockDim.x + threadIdx.x;
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int64_t step = static_cast<int64_t>(blockDim.x) * gridDim.x;
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for (int64_t index = begin; index < pre_dim; index += step) {
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int64_t pos = static_cast<int64_t>(index * max_valid_num);
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int64_t nan_cnt = nan_counts[index];
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if (nan_cnt == stride) {
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median_val[index] = -1;
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output[index] = nan_val;
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} else {
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int64_t nan_k =
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nan_cnt > 0 ? static_cast<int64_t>(stride - nan_cnt) : max_valid_num;
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int64_t row_pos = static_cast<int64_t>(nan_k >> 1);
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pos += row_pos;
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if (nan_k & 1) {
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median_val[index] = sort_indices_ptr[pos];
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output[index] = sort_out_ptr[pos];
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} else {
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T median_val_left = pos > 0 ? sort_out_ptr[pos - 1] : sort_out_ptr[pos];
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median_val[index] =
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pos > 0 ? sort_indices_ptr[pos - 1] : sort_indices_ptr[pos];
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output[index] = median_val_left;
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}
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}
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}
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}
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template <typename T, typename Context>
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void ProcessMedianKernel(const Context& dev_ctx,
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const DenseTensor& x,
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const std::string& mode,
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bool ignore_nan,
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DenseTensor* out,
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DenseTensor* median_index) {
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#ifdef PADDLE_WITH_CUDA
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const auto& exec_policy = thrust::cuda::par.on(dev_ctx.stream());
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#else
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const auto& exec_policy = thrust::hip::par.on(dev_ctx.stream());
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#endif
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auto stream = dev_ctx.stream();
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const T* x_data = x.data<T>();
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T* out_data = dev_ctx.template Alloc<T>(out);
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int64_t* m_data = dev_ctx.template Alloc<int64_t>(median_index);
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int64_t numel = x.numel();
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auto x_dim = x.dims();
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int x_rank = x_dim.size();
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int64_t stride = x_dim[x_rank - 1];
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PADDLE_ENFORCE_NE(stride,
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0,
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common::errors::InvalidArgument(
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"The input Tensor x's shape[-1] should not "
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"be 0, but shape is %s now.",
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x_dim));
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int64_t pre_dim = numel / stride;
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DenseTensor nan_counts;
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DenseTensor nan_indices;
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int64_t* nan_counts_ptr;
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int64_t* nan_indices_ptr;
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int64_t max_valid_num = 0;
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nan_counts.Resize({pre_dim});
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dev_ctx.template Alloc<int64_t>(&nan_counts);
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nan_counts_ptr = nan_counts.data<int64_t>();
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nan_indices.Resize({pre_dim});
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dev_ctx.template Alloc<int64_t>(&nan_indices);
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funcs::SetConstant<GPUContext, int64_t> set_const;
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set_const(dev_ctx, &nan_indices, numel);
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nan_indices_ptr = nan_indices.data<int64_t>();
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int block_size = std::min(ELEMWISE_MAX_BLOCK_DIM, stride);
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int64_t grid_size = pre_dim;
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int64_t max_grid_dim = dev_ctx.GetCUDAMaxGridDimSize()[0];
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grid_size = std::min(grid_size, max_grid_dim);
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KernelNanCounts<T><<<grid_size, block_size, 0, stream>>>(
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x_data, numel, pre_dim, stride, nan_counts_ptr, nan_indices_ptr);
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auto nan_stat_mem_cpu = memory_utils::Alloc(CPUPlace(), sizeof(int64_t) * 2);
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int64_t* nan_stat_cpu_ptr =
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reinterpret_cast<int64_t*>(nan_stat_mem_cpu->ptr());
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int64_t sum =
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thrust::reduce(exec_policy, nan_counts_ptr, nan_counts_ptr + pre_dim);
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nan_stat_cpu_ptr[0] = sum;
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auto min_nan_ptr = thrust::min_element(
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exec_policy, nan_counts_ptr, nan_counts_ptr + pre_dim);
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memory_utils::Copy(CPUPlace(),
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nan_stat_cpu_ptr + 1,
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dev_ctx.GetPlace(),
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min_nan_ptr,
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sizeof(int64_t),
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stream);
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T nan_val = std::numeric_limits<T>::quiet_NaN();
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if (nan_stat_cpu_ptr[0] == numel) {
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funcs::SetConstant<Context, T> set_nan;
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set_nan(dev_ctx, out, nan_val);
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funcs::SetConstant<Context, int64_t> set_negatvie;
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set_negatvie(dev_ctx, median_index, static_cast<int64_t>(0));
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return;
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}
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max_valid_num = stride - nan_stat_cpu_ptr[1];
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int64_t sort_k = ignore_nan ? max_valid_num : ((stride >> 1) + 1);
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bool is_ori_odd = stride & 1;
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DenseTensor sort_out, sort_indices;
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auto sort_dim = x.dims();
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int64_t rank = sort_dim.size();
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sort_dim[rank - 1] = sort_k;
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sort_out.Resize(sort_dim);
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sort_indices.Resize(sort_dim);
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dev_ctx.template Alloc<T>(&sort_out);
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T* sort_out_ptr = sort_out.data<T>();
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dev_ctx.template Alloc<int64_t>(&sort_indices);
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int64_t* sort_indices_ptr = sort_indices.data<int64_t>();
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TopkKernel<T, Context>(
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dev_ctx, x, Scalar(sort_k), -1, false, true, &sort_out, &sort_indices);
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T div_factor = static_cast<T>(2.0);
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auto config = backends::gpu::GetGpuLaunchConfig1D(dev_ctx, pre_dim);
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if (ignore_nan) {
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if (mode == "avg") {
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CalcNanmedianMeanKernel<T>
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<<<config.block_per_grid.x, config.thread_per_block.x, 0, stream>>>(
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sort_out_ptr,
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sort_indices_ptr,
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nan_counts_ptr,
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m_data,
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out_data,
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is_ori_odd,
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pre_dim,
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max_valid_num,
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stride,
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div_factor,
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nan_val);
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} else { // mode == "min"
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CalcNanmedianMinKernel<T>
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<<<config.block_per_grid.x, config.thread_per_block.x, 0, stream>>>(
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sort_out_ptr,
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sort_indices_ptr,
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nan_counts_ptr,
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m_data,
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out_data,
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is_ori_odd,
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pre_dim,
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max_valid_num,
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stride,
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div_factor,
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nan_val);
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}
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} else {
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if (mode == "avg") {
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CalcMedianMeanKernel<T>
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<<<config.block_per_grid.x, config.thread_per_block.x, 0, stream>>>(
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sort_out_ptr,
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sort_indices_ptr,
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nan_counts_ptr,
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nan_indices_ptr,
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nan_val,
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m_data,
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out_data,
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div_factor,
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is_ori_odd,
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pre_dim,
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sort_k);
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} else { // mode == "min"
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CalcMedianMinKernel<T>
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<<<config.block_per_grid.x, config.thread_per_block.x, 0, stream>>>(
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sort_out_ptr,
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sort_indices_ptr,
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nan_counts_ptr,
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nan_indices_ptr,
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nan_val,
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m_data,
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out_data,
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div_factor,
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is_ori_odd,
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pre_dim,
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sort_k);
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}
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}
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}
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template <typename T, typename Context>
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void MedianKernel(const Context& dev_ctx,
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const DenseTensor& x,
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const IntArray& axes,
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bool keepdim,
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const std::string& mode,
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DenseTensor* out,
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DenseTensor* median_index) {
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if (x.numel() == 0) {
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Full<T, Context>(dev_ctx, out->dims(), NAN, out);
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Full<int64_t, Context>(dev_ctx, median_index->dims(), 0, median_index);
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return;
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}
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DenseTensor tmp_x;
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auto rank = x.dims().size();
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if ((axes.size() == 0) || rank <= 1) {
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tmp_x = x;
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tmp_x.Resize({x.numel()});
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} else {
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funcs::PreprocessMedianKernel<T, Context>(dev_ctx, x, axes, &tmp_x);
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}
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ProcessMedianKernel<T, Context>(
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dev_ctx, tmp_x, mode, false, out, median_index);
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}
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} // namespace phi
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PD_REGISTER_KERNEL(median,
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GPU,
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ALL_LAYOUT,
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phi::MedianKernel,
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float,
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double,
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int,
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int64_t,
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phi::float16,
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phi::bfloat16) {
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kernel->OutputAt(1).SetDataType(phi::DataType::INT64);
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}
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