163 lines
6.3 KiB
C++
163 lines
6.3 KiB
C++
/* Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#pragma once
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#include "paddle/phi/backends/gpu/gpu_context.h"
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#include "paddle/phi/backends/gpu/gpu_launch_config.h"
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#include "paddle/phi/kernels/funcs/aligned_vector.h"
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#define VecBytes 16
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namespace phi {
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namespace funcs {
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namespace sparse {
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/**
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* brief: scatter add
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* input: the inputs
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* unique_value: refer to UpdateIndexKernel notes
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* out_index: the output feature index
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* non_zero_num: the number of output features
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* rulebook_len: the length of rulebook
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* channels: the output channel size
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* out: the outputs
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**/
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template <typename T, int VecSize>
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__global__ void ScatterKernel(const T* input,
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const int* unique_value,
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const int* out_index,
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const int non_zero_num,
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const int rulebook_len,
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const int channels,
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T* out) {
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int64_t tid =
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static_cast<int64_t>(threadIdx.x) +
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static_cast<int64_t>(blockIdx.x) * static_cast<int64_t>(blockDim.x);
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const int vec_channels = channels / VecSize;
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using LoadT = AlignedVector<T, VecSize>;
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using StoreT = AlignedVector<T, VecSize>;
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for (int i = tid; i < non_zero_num * vec_channels;
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i += gridDim.x * blockDim.x) {
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int indices_i = i / vec_channels;
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int channels_i = i - indices_i * vec_channels;
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int start = unique_value[indices_i];
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int end = indices_i == non_zero_num - 1 ? rulebook_len
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: unique_value[indices_i + 1];
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// max(end-start) = kernel_size
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StoreT sums = {static_cast<T>(0)};
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for (int j = start; j < end; j++) {
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const int out_feature_i = out_index[j];
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LoadT vec_in;
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Load<T, VecSize>(input + out_feature_i * channels + channels_i * VecSize,
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&vec_in);
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#pragma unroll
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for (int k = 0; k < VecSize; k++) {
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sums[k] += vec_in[k];
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}
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}
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Store<T, VecSize>(sums, out + indices_i * channels + channels_i * VecSize);
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}
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}
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// scatter's index has been grouped in advance
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// index_counts record the count of each group
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// index_groups save the index of each group
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template <typename T, int VecSize>
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__global__ void ScatterKernelV2(const T* input,
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const int* index_counts,
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const int* index_groups,
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const int non_zero_num,
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const int kernel_size,
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const int channels,
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const int buffer_counts,
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T* out) {
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int64_t tid =
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static_cast<int64_t>(threadIdx.x) +
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static_cast<int64_t>(blockIdx.x) * static_cast<int64_t>(blockDim.x);
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const int vec_channels = channels / VecSize;
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using LoadT = AlignedVector<T, VecSize>;
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using StoreT = AlignedVector<T, VecSize>;
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for (int i = tid; i < non_zero_num * vec_channels;
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i += gridDim.x * blockDim.x) {
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int indices_i = i / vec_channels;
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int channels_i = i - indices_i * vec_channels;
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StoreT sums = {static_cast<T>(0)};
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Load<T, VecSize>(out + indices_i * channels + channels_i * VecSize, &sums);
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for (int it = 0; it < buffer_counts; it++) {
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int len = index_counts[indices_i + it * non_zero_num];
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const int group_offset = it * kernel_size * non_zero_num;
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for (int j = 0; j < len; j++) {
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const int out_feature_i =
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index_groups[indices_i * kernel_size + j + group_offset];
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LoadT vec_in;
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Load<T, VecSize>(
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input + out_feature_i * channels + channels_i * VecSize, &vec_in);
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#pragma unroll
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for (int k = 0; k < VecSize; k++) {
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sums[k] += vec_in[k];
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}
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}
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}
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Store<T, VecSize>(sums, out + indices_i * channels + channels_i * VecSize);
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}
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}
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template <typename T>
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void ScatterV2(const GPUContext& dev_ctx,
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const T* input,
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const int* index_counts,
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const int* index_groups,
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const int non_zero_num,
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const int kernel_size,
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const int channels,
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const int buffer_counts,
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T* output) {
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const int VecSize = VecBytes / sizeof(T);
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if (channels % VecSize == 0) {
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auto config = phi::backends::gpu::GetGpuLaunchConfig1D(
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dev_ctx, non_zero_num * channels / VecSize, 1);
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ScatterKernelV2<T, VecSize><<<config.block_per_grid.x,
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config.thread_per_block.x,
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0,
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dev_ctx.stream()>>>(input,
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index_counts,
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index_groups,
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non_zero_num,
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kernel_size,
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channels,
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buffer_counts,
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output);
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} else {
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auto config = phi::backends::gpu::GetGpuLaunchConfig1D(
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dev_ctx, non_zero_num * channels, 1);
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ScatterKernelV2<T, 1><<<config.block_per_grid.x,
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config.thread_per_block.x,
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0,
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dev_ctx.stream()>>>(input,
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index_counts,
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index_groups,
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non_zero_num,
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kernel_size,
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channels,
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buffer_counts,
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output);
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}
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}
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} // namespace sparse
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} // namespace funcs
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} // namespace phi
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