wehub-resource-sync
116 lines
4.2 KiB
C++
116 lines
4.2 KiB
C++
// Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "paddle/phi/kernels/deformable_conv_kernel.h"
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#include "paddle/phi/backends/xpu/enforce_xpu.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/kernels/full_kernel.h"
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namespace phi {
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template <typename T, typename Context>
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void DeformableConvKernel(const Context& dev_ctx,
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const DenseTensor& x,
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const DenseTensor& offset,
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const DenseTensor& filter,
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const optional<DenseTensor>& mask,
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const std::vector<int>& strides,
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const std::vector<int>& paddings,
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const std::vector<int>& dilations,
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int deformable_groups,
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int groups,
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int im2col_step,
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DenseTensor* out) {
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if (x.numel() == 0 || filter.numel() == 0) {
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Full<T, Context>(dev_ctx, out->dims(), 0, out);
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return;
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}
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dev_ctx.template Alloc<T>(out);
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if (backends::xpu::get_xpu_version(dev_ctx.GetPlace().GetDeviceId()) ==
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backends::xpu::XPUVersion::XPU1) {
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PADDLE_ENFORCE_EQ(
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deformable_groups == 1,
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true,
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errors::InvalidArgument(("XPU1 only support deformable_groups == 1 in "
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"deformable_conv op.")));
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PADDLE_ENFORCE_EQ(
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groups == 1,
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true,
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errors::InvalidArgument(
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("XPU1 only support groups == 1 in deformable_conv op.")));
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}
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PADDLE_ENFORCE_EQ(filter.dims()[2] <= 8 && filter.dims()[3] <= 8,
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true,
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errors::InvalidArgument(
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"Filter high and weight should less than 8 on xpu "
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"in deformable_conv op."));
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const int64_t batch_size = x.dims()[0];
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std::vector<int64_t> output_shape_vec(vectorize(out->dims()));
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const T* input_ptr = x.data<T>();
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const T* filter_ptr = filter.data<T>();
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const float* offset_ptr = offset.data<T>();
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const float* mask_ptr = mask ? mask->data<T>() : nullptr;
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T* output_prt = out->data<T>();
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// set zeros for d_table_data
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const int zero = 0;
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int r = xpu::constant<T>(dev_ctx.x_context(), output_prt, out->numel(), zero);
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PADDLE_ENFORCE_XDNN_SUCCESS(r, "constant");
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int64_t input_dim = x.numel() / x.dims()[0];
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int64_t input_offset_dim = offset.numel() / offset.dims()[0];
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int64_t input_mask_dim = mask->numel() / mask->dims()[0];
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int64_t output_dim =
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output_shape_vec[1] * output_shape_vec[2] * output_shape_vec[3];
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std::vector<int64_t> ksize{filter.dims()[2], filter.dims()[3]};
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int64_t n = static_cast<int64_t>(im2col_step);
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int64_t c = x.dims()[1];
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int64_t h = x.dims()[2];
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int64_t w = x.dims()[3];
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int64_t f = filter.dims()[0];
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for (int64_t i = 0; i < batch_size / n; ++i) {
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int r = xpu::deformable_conv<float, float, float, int>(
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dev_ctx.x_context(),
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input_ptr + i * n * input_dim,
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filter_ptr,
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offset_ptr + i * n * input_offset_dim,
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mask_ptr + i * n * input_mask_dim,
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output_prt + i * n * output_dim,
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n,
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c,
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h,
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w,
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f,
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ksize,
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std::vector<int64_t>{strides.begin(), strides.end()},
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std::vector<int64_t>{paddings.begin(), paddings.end()},
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std::vector<int64_t>{dilations.begin(), dilations.end()},
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groups,
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deformable_groups,
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nullptr,
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nullptr,
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nullptr,
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true);
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PADDLE_ENFORCE_XDNN_SUCCESS(r, "deformable_conv");
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}
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}
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} // namespace phi
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PD_REGISTER_KERNEL(
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deformable_conv, XPU, ALL_LAYOUT, phi::DeformableConvKernel, float) {}
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