wehub-resource-sync
395 lines
13 KiB
Python
395 lines
13 KiB
Python
# Copyright (c) 2025 PaddlePaddle Authors. All Rights Reserved.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# The file has been adapted from DeepSeek DeepGEMM project
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# Copyright (c) 2025 DeepSeek
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# Licensed under the MIT License - https://github.com/deepseek-ai/DeepGEMM/blob/main/LICENSE
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from __future__ import annotations
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import math
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import os
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from functools import cache
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import paddle
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from ..jit import FP8GemmRuntime, build
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from .runtime import (
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GemmType,
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make_2d_tma_a_desc,
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make_2d_tma_b_desc,
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make_2d_tma_d_desc,
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make_2d_tma_scales_desc,
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)
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from .utils import (
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ceil_div,
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get_col_major_tma_aligned_tensor,
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get_m_alignment_for_contiguous_layout,
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get_num_sms,
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)
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global_empty_tensor = paddle.empty([0], dtype=paddle.int32)
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# Todo: Use default stream to accelerate CPU time. Optimize here if use multistream to launch gemm kernel.
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global_stream = paddle.device.current_stream().stream_base.cuda_stream
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def is_tma_multicast_legal(
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shape_dim: int,
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block_dim: int,
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num_tma_multicast: int,
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num_sms: int,
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require_divisible: bool = False,
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) -> bool:
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divisible = (
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ceil_div(shape_dim, block_dim) % num_tma_multicast == 0
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or not require_divisible
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)
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return divisible and num_sms % num_tma_multicast == 0
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def get_swizzle_mode(block_n: int) -> int:
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elem_size = 2
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for mode_bytes in (128, 64, 32):
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if (block_n * elem_size) % mode_bytes == 0:
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return mode_bytes
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return 0
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def get_block_n_padding_for_smem_d(block_n: int) -> int:
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# NOTES: padding is for solving bank conflicts, but wastes shared memory space
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elem_size, requirement = 2, (4, 8)
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bank_stride = (block_n * elem_size) // 4
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padding = (requirement[0] - bank_stride) % requirement[1]
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return (
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((padding + requirement[1]) if padding < 0 else padding) * 4
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) // elem_size
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def get_smem_config(
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num_stages: int,
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k: int,
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block_m: int,
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block_n: int,
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block_k: int = 128,
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is_fp32_out: bool = False,
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is_wgrad: bool = False,
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) -> tuple[int, int, int]:
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assert block_k == 128
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# Try swizzle first, as it does not waste shared memory
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swizzle_mode = get_swizzle_mode(block_n)
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block_n_padding = (
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get_block_n_padding_for_smem_d(block_n) if swizzle_mode == 0 else 0
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)
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# NOTES: `scales_b` in a total manner or per-stage manner
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smem_d = block_m * (block_n + block_n_padding) * (4 if is_fp32_out else 2)
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smem_a_per_stage = block_m * block_k
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smem_scales_a_per_stage = block_m * 4
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smem_b_per_stage = block_n * block_k
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smem_scales_b_per_stage = (
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ceil_div(block_n * 4, block_k) * block_k if is_wgrad else 0
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)
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smem_scales_b = ceil_div(k, block_k) * 4 if not is_wgrad else 0
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smem_barrier = num_stages * 8 * 2
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smem_size = 0
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smem_size += smem_d
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smem_size += num_stages * smem_a_per_stage
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smem_size += num_stages * smem_scales_a_per_stage
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smem_size += num_stages * smem_b_per_stage
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smem_size += num_stages * smem_scales_b_per_stage
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smem_size += (
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ceil_div(smem_scales_b * (1 if block_k % block_n == 0 else 2), 8) * 8
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)
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smem_size += smem_barrier
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# Swizzle and padding are not compatible
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assert int(swizzle_mode > 0) + int(block_n_padding > 0) <= 1
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return smem_size, swizzle_mode, block_n_padding
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@cache
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def get_best_configs(
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m: int,
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n: int,
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k: int,
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num_groups: int,
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num_sms: int,
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is_grouped_contiguous: bool = False,
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is_grouped_masked: bool = False,
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is_fp32_out: bool = False,
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is_wgrad: bool = False,
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) -> tuple[int, int, int, int, tuple[int, bool], tuple[int, int, int]]:
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if not is_grouped_contiguous:
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block_ms = (
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64,
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128,
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) + ((256,) if not is_fp32_out else ())
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else:
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block_ms = (get_m_alignment_for_contiguous_layout(),)
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block_ns = tuple(range(16, 129, 8)) + (
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(
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136,
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152,
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)
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if is_wgrad
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else (
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144,
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160,
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)
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)
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# Avoid bank conflicts for FP32 output
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if is_fp32_out:
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block_ns = [x for x in block_ns if x % 16 == 8]
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fix_wave_saturate = lambda x: num_sms if x == 0 else x
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get_num_waves = lambda bm, bn: (
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ceil_div(ceil_div(m, bm) * ceil_div(n, bn) * num_groups, num_sms)
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if bm
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else None
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)
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get_last_wave_util = lambda bm, bn: fix_wave_saturate(
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(ceil_div(m, bm) * ceil_div(n, bn) * num_groups) % num_sms
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)
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# Decide block sizes by waves
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best_block_m, best_block_n = None, None
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for block_m in block_ms:
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# NOTES: the block sizes cannot be too large, so at least one dim less than 128
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for block_n in filter(lambda bn: block_m <= 128 or bn <= 128, block_ns):
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success = False
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num_waves, best_num_waves = (
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get_num_waves(block_m, block_n),
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get_num_waves(best_block_m, best_block_n),
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)
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if best_block_m is None or best_block_n is None:
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success = True
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elif num_waves < best_num_waves:
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success = True
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elif num_waves == best_num_waves:
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# Check last wave utilization
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util = get_last_wave_util(block_m, block_n)
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best_util = get_last_wave_util(best_block_m, best_block_n)
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success = util > best_util
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if util == best_util:
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# Case 1: same `block_m`, smaller `block_n` (wasted)
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success |= (
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block_m == best_block_m and block_n < best_block_n
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)
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# Case 2: same `block_n`, smaller `block_m` (wasted)
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success |= (
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block_n == best_block_n and block_m < best_block_m
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)
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# Case 3: different for both `block_m` and `block_n`, `block_n` larger is better
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success |= (
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block_m != best_block_m and block_n > best_block_n
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)
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best_block_m, best_block_n = (
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(block_m, block_n) if success else (best_block_m, best_block_n)
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)
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assert best_block_m is not None and best_block_n is not None
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# Always pick the longest one
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# NOTES: for double B scales, the best number of stages may be reduced
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best_num_stages, best_smem_config, sm90_capacity = None, None, 232448
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stage_candidates = tuple(
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filter(lambda s: s <= max(k // 128, 1), (8, 7, 6, 5, 4, 3, 2, 1))
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)
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if 128 % best_block_n != 0 and 128 // math.gcd(128, best_block_n) <= 4:
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# Unrolling both stages and `num_former_iters` will cause large code size
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stage_candidates = tuple(
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filter(lambda s: s <= max(k // 128, 1), (4, 3, 2, 1))
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)
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for num_stages in stage_candidates:
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best_smem_config = get_smem_config(
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num_stages,
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k,
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best_block_m,
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best_block_n,
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is_fp32_out=is_fp32_out,
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is_wgrad=is_wgrad,
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)
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if best_smem_config[0] <= sm90_capacity:
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best_num_stages = num_stages
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break
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assert best_smem_config is not None
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assert best_num_stages is not None
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# Decide the number of TMA multicasts and whether broadcast on A
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best_tma_multicast_config = (1, True)
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# Try to multicast on the larger block side first
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# NOTES: currently, grouped masked GEMM only supports multicast on A and requires the number of blocks in the N-direction to be even
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is_multicast_legal = {
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"A": is_tma_multicast_legal(
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n, best_block_n, 2, num_sms, is_grouped_masked
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),
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"B": is_tma_multicast_legal(m, best_block_m, 2, num_sms)
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and not is_grouped_masked,
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}
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for i in ("A", "B") if best_block_m > best_block_n else ("B", "A"):
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if m >= 512 and is_multicast_legal[i]:
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best_tma_multicast_config = (2, i == "A")
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break
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# Recompute the minimal number of SMs required
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# NOTES: less L2 cache usage and less GPU frequency drop
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num_waves = get_num_waves(best_block_m, best_block_n)
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num_min_sms = ceil_div(
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ceil_div(m, best_block_m) * ceil_div(n, best_block_n) * num_groups,
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num_waves,
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)
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num_min_sms = (
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ceil_div(num_min_sms, best_tma_multicast_config[0])
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* best_tma_multicast_config[0]
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)
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assert num_min_sms <= num_sms
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return (
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num_min_sms,
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best_block_m,
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best_block_n,
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best_num_stages,
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best_tma_multicast_config,
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best_smem_config,
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)
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def gemm_fp8_fp8_bf16_nt(
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lhs: tuple[paddle.Tensor, paddle.Tensor],
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rhs: tuple[paddle.Tensor, paddle.Tensor],
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out: paddle.Tensor,
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num_sms: int | None = None,
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) -> None:
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"""
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Perform a normal GEMM with FP8 inputs and BF16 output, with 1x128 LHS scaling and 128x128 RHS scaling.
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Requirements:
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LHS, RHS, and output tensors must be contiguous in dimension 1, i.e., strides[1] = 1.
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The strides[0] of LHS and RHS must be a multiple of 16, and the strides[0] of output must be a multiple of 8.
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RHS and RHS scaling factors are required to be transposed.
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The LHS scaling tensor requires a TMA-aligned transposed format, if your input does not match the requirement,
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this function will do a transposing with a set of slow PaddlePaddle operations.
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Arguments:
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lhs: the first element is an FP8 tensor (typed `paddle.float8_e4m3fn`) of shape `[m, k]`,
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the second element is an FP32 1x128 scaling tensor for LHS of shape `[m, ⌈k / 128⌉]`.
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rhs: the first element is an FP8 tensor (typed `paddle.float8_e4m3fn`) of shape `[n, k]`,
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the second element is an FP32 128x128 scaling tensor for RHS of shape `[⌈n / 128⌉, ⌈k / 128⌉]`.
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out: the BF16 output tensor of shape `[m, n]`, representing the result.
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"""
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lhs, lhs_scales = lhs
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rhs, rhs_scales = rhs
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m, k = lhs.shape
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n, k_ = rhs.shape
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m_, n_ = out.shape
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# Type and shape checks
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assert m == m_ and n == n_ and k == k_
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assert n > 0 and k > 0
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assert lhs_scales.shape == [m, ceil_div(k, 128)]
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assert rhs_scales.shape == [ceil_div(n, 128), ceil_div(k, 128)]
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assert (
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lhs.dtype == paddle.float8_e4m3fn and lhs_scales.dtype == paddle.float32
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)
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assert (
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rhs.dtype == paddle.float8_e4m3fn and rhs_scales.dtype == paddle.float32
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)
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assert out.dtype == paddle.bfloat16
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assert lhs.strides[1] == 1 and out.strides[1] == 1 and rhs.strides[1] == 1
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# LHS scales must be transposed for TMA loads, but not for RHS scales
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# NOTES: `get_col_major_tma_aligned_tensor` may launch a kernel if not processed by previous kernels
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lhs_scales = get_col_major_tma_aligned_tensor(lhs_scales)
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assert rhs_scales.is_contiguous()
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# Do nothing if `m` is zero
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if m == 0:
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return
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# K must be aligned to 128
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aligned_k = ceil_div(k, 128) * 128
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# Auto-tuning with compilation
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if num_sms is None:
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num_sms = get_num_sms()
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num_sms, block_m, block_n, num_stages, tma_multicast_config, smem_config = (
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get_best_configs(m, n, k, 1, num_sms)
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)
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if int(os.getenv("DG_JIT_KERNELS_DEBUG", 0)):
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print(
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f"Auto-tuned gemm_fp8_fp8_bf16_nt as num_sms={num_sms}, block_m={block_m}, block_n={block_n}"
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)
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block_k = 128
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num_tma_threads = 128
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num_math_threads_per_group = 128
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tensor_map_a = make_2d_tma_a_desc(
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GemmType.Normal, lhs, m, k, lhs.strides[0], block_m, block_k, 1
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)
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tensor_map_b = make_2d_tma_b_desc(
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GemmType.Normal, rhs, n, k, rhs.strides[0], block_n, block_k, 1
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)
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tensor_map_d = make_2d_tma_d_desc(
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GemmType.Normal,
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out,
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m,
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n,
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out.strides[0],
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block_m,
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block_n,
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1,
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smem_config[1],
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)
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tensor_map_scales_a = make_2d_tma_scales_desc(
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GemmType.Normal, lhs_scales, m, k, block_m, block_k, 1
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)
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kwargs = {
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# Templated arguments
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"GEMM_TYPE": GemmType.Normal,
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"NUM_TMA_THREADS": num_tma_threads,
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"NUM_MATH_THREADS_PER_GROUP": num_math_threads_per_group,
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"M": m,
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"N": n,
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"K": aligned_k,
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"NUM_GROUPS": 1,
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"BLOCK_M": block_m,
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"BLOCK_N": block_n,
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"BLOCK_K": block_k,
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"SWIZZLE_D_MODE": smem_config[1],
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"BLOCK_N_PADDING": smem_config[2],
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"NUM_STAGES": num_stages,
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"NUM_TMA_MULTICAST": tma_multicast_config[0],
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"IS_TMA_MULTICAST_ON_A": tma_multicast_config[1],
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# Runtime arguments
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"SCALES_B": rhs_scales,
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"GROUPED_LAYOUT": global_empty_tensor,
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"NUM_SMS": num_sms,
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"SMEM_SIZE": smem_config[0],
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"TENSOR_MAP_A": tensor_map_a,
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"TENSOR_MAP_B": tensor_map_b,
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"TENSOR_MAP_SCALES_A": tensor_map_scales_a,
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"TENSOR_MAP_D": tensor_map_d,
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"STREAM": global_stream,
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"DEVICE_INDEX": out.place.gpu_device_id(),
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}
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# Generate, build and run the kernel
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runtime = build("gemm_fp8_fp8_bf16_nt", FP8GemmRuntime, kwargs)
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runtime(**kwargs)
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