wehub-resource-sync
333 lines
12 KiB
C++
333 lines
12 KiB
C++
// Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "paddle/phi/kernels/conv_kernel.h"
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#include "paddle/phi/backends/xpu/enforce_xpu.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/kernels/cpu/conv_util.h"
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#include "paddle/phi/kernels/full_kernel.h"
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#include "paddle/phi/kernels/xpu/conv_utils_xpu.h"
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#include "paddle/phi/kernels/xpu/xpu_api_wrapper.h"
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#ifdef PADDLE_WITH_XPU_XRE5
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#include "xpudnn/xpudnn.h"
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namespace xpudnn = baidu::xpu::xpudnn;
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#endif
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namespace phi {
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template <typename T, typename Context>
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void ConvKernel(const Context& dev_ctx,
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const DenseTensor& input,
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const DenseTensor& filter,
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const std::vector<int>& strides_t,
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const std::vector<int>& paddings_t,
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const std::string& padding_algorithm,
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const std::vector<int>& dilations_t,
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int groups,
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const std::string& data_format,
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DenseTensor* out) {
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if (input.numel() == 0) {
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Full<T, Context>(dev_ctx, out->dims(), 0, out);
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return;
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}
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using XPUType = typename XPUTypeTrait<T>::Type;
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std::vector<int64_t> paddings(paddings_t.begin(), paddings_t.end());
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std::vector<int64_t> dilations(dilations_t.begin(), dilations_t.end());
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std::vector<int64_t> strides(strides_t.begin(), strides_t.end());
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// The filter will be reshaped in the calculations,
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// so here use an assignment operation,
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// that avoids modifying the variable in the Scope.
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dev_ctx.template Alloc<T>(out);
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PADDLE_ENFORCE_EQ(
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data_format == "NDHWC",
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false,
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common::errors::InvalidArgument(
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("XPU does not support data_format is NDHWC in conv op.")));
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DDim in_data_dims = slice_ddim(input.dims(), 2, input.dims().size());
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DDim filter_data_dims = slice_ddim(filter.dims(), 2, filter.dims().size());
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std::vector<int64_t> ksize = vectorize<int64_t>(filter_data_dims);
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UpdatePaddingAndDilation<int64_t>(
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&paddings, &dilations, padding_algorithm, in_data_dims, strides, ksize);
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int64_t batch_size = input.dims()[0];
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int64_t img_c = input.dims()[1];
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int64_t img_h = input.dims()[2];
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int64_t img_w = input.dims()[3];
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int64_t f = filter.dims()[0];
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bool is_nchw = true;
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if (data_format == "NHWC") {
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img_c = input.dims()[3];
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img_h = input.dims()[1];
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img_w = input.dims()[2];
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is_nchw = false;
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}
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const XPUType* input_data = reinterpret_cast<const XPUType*>(input.data<T>());
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const XPUType* filter_data =
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reinterpret_cast<const XPUType*>(filter.data<T>());
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XPUType* output_data = reinterpret_cast<XPUType*>(out->data<T>());
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xpu::ctx_guard RAII_GUARD(dev_ctx.x_context());
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XPUType* filter_data_tmp;
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const XPUType* filter_data_ptr = filter_data;
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if (data_format == "NHWC") {
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filter_data_tmp = RAII_GUARD.alloc<XPUType>(filter.numel());
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PADDLE_ENFORCE_XDNN_NOT_NULL(filter_data_tmp);
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std::vector<int64_t> filter_shape = vectorize<int64_t>(filter.dims());
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int r = xpu::transpose<XPUType>(dev_ctx.x_context(),
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filter_data,
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filter_data_tmp,
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filter_shape,
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{0, 2, 3, 1});
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PADDLE_ENFORCE_XDNN_SUCCESS(r, "transpose");
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filter_data_ptr = reinterpret_cast<const XPUType*>(filter_data_tmp);
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}
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int fc_calc_type = GetConvCalcType<XPUType>();
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PD_VISIT_XPU_CONV_TYPES(XPUType, fc_calc_type, "conv2d", [&] {
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#ifdef PADDLE_WITH_XPU_XRE5
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int ret = xpudnn::conv2d_fusion<XPUType, XPUType, XPUType, TGEMM>(
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dev_ctx.x_context(),
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input_data,
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filter_data_ptr,
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output_data,
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batch_size,
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img_c,
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img_h,
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img_w,
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f,
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ksize,
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strides,
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paddings,
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dilations,
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groups,
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nullptr,
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nullptr,
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nullptr,
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is_nchw,
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nullptr,
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nullptr,
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xpu::Activation_t::LINEAR);
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PADDLE_ENFORCE_XDNN_SUCCESS(ret, "conv2d_fusion");
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#else
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int r = xpu::conv2d<XPUType, XPUType, XPUType, TGEMM>(dev_ctx.x_context(),
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input_data,
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filter_data_ptr,
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output_data,
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batch_size,
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img_c,
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img_h,
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img_w,
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f,
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ksize,
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strides,
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paddings,
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dilations,
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groups,
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nullptr,
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nullptr,
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nullptr,
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is_nchw);
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PADDLE_ENFORCE_XDNN_SUCCESS(r, "conv2d");
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#endif
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});
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}
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template <typename T, typename Context>
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void DepthwiseConvKernel(const Context& dev_ctx,
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const DenseTensor& input,
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const DenseTensor& filter,
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const std::vector<int>& strides,
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const std::vector<int>& paddings,
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const std::string& padding_algorithm,
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int groups,
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const std::vector<int>& dilations,
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const std::string& data_format,
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DenseTensor* out) {
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ConvKernel<T, Context>(dev_ctx,
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input,
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filter,
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strides,
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paddings,
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padding_algorithm,
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dilations,
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groups,
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data_format,
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out);
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}
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template <typename T, typename Context>
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void Conv3DKernel(const Context& dev_ctx,
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const DenseTensor& input,
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const DenseTensor& filter,
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const std::vector<int>& strides_t,
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const std::vector<int>& paddings_t,
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const std::string& padding_algorithm,
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int groups,
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const std::vector<int>& dilations_t,
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const std::string& data_format,
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DenseTensor* out) {
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if (input.numel() == 0 || out->numel() == 0) {
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dev_ctx.template Alloc<T>(out);
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return;
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}
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using XPUType = typename XPUTypeTrait<T>::Type;
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std::vector<int64_t> paddings(paddings_t.begin(), paddings_t.end());
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std::vector<int64_t> dilations(dilations_t.begin(), dilations_t.end());
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std::vector<int64_t> strides(strides_t.begin(), strides_t.end());
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// The filter will be reshaped in the calculations,
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// so here use an assignment operation,
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// that avoids modifying the variable in the Scope.
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dev_ctx.template Alloc<T>(out);
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DDim in_data_dims;
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if (data_format == "NDHWC") {
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in_data_dims = slice_ddim(input.dims(), 1, input.dims().size() - 1);
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} else {
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in_data_dims = slice_ddim(input.dims(), 2, input.dims().size());
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}
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DDim filter_data_dims = slice_ddim(filter.dims(), 2, filter.dims().size());
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std::vector<int64_t> ksize = vectorize<int64_t>(filter_data_dims);
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UpdatePaddingAndDilation<int64_t>(
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&paddings, &dilations, padding_algorithm, in_data_dims, strides, ksize);
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int64_t batch_size = input.dims()[0];
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int64_t img_c = input.dims()[1];
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int64_t img_d = input.dims()[2];
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int64_t img_h = input.dims()[3];
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int64_t img_w = input.dims()[4];
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int64_t f = filter.dims()[0];
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bool is_ncdhw = true;
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if (data_format == "NDHWC") {
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img_c = input.dims()[4];
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img_d = input.dims()[1];
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img_h = input.dims()[2];
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img_w = input.dims()[3];
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is_ncdhw = false;
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}
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XPUType* output_data = reinterpret_cast<XPUType*>(out->data<T>());
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const XPUType* filter_data =
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reinterpret_cast<const XPUType*>(filter.data<T>());
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const XPUType* input_data = reinterpret_cast<const XPUType*>(input.data<T>());
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xpu::ctx_guard RAII_GUARD(dev_ctx.x_context());
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XPUType* filter_data_tmp;
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const XPUType* filter_data_ptr = filter_data;
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if (data_format == "NDHWC") {
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filter_data_tmp = RAII_GUARD.alloc<XPUType>(filter.numel());
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PADDLE_ENFORCE_XDNN_NOT_NULL(filter_data_tmp);
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std::vector<int64_t> filter_shape = vectorize<int64_t>(filter.dims());
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int r = xpu::transpose<XPUType>(dev_ctx.x_context(),
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filter_data,
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filter_data_tmp,
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filter_shape,
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{0, 2, 3, 4, 1});
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PADDLE_ENFORCE_XDNN_SUCCESS(r, "transpose");
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filter_data_ptr = reinterpret_cast<const XPUType*>(filter_data_tmp);
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}
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int fc_calc_type = GetConvCalcType<XPUType>();
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PD_VISIT_XPU_CONV_TYPES(XPUType, fc_calc_type, "conv3d", [&] {
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#ifdef PADDLE_WITH_XPU_XRE5
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using XPUTypeFP16 = typename XPUTypeTrait<phi::float16>::Type;
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using RealTGEMM = std::conditional_t<std::is_same_v<XPUType, XPUTypeFP16> &&
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std::is_same_v<TGEMM, float>,
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XPUTypeFP16,
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TGEMM>;
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int ret = xpudnn::conv3d_fusion<XPUType, XPUType, XPUType, RealTGEMM>(
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dev_ctx.x_context(),
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input_data,
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filter_data_ptr,
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output_data,
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batch_size,
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img_c,
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img_d,
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img_h,
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img_w,
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f,
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ksize,
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strides,
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paddings,
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dilations,
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groups,
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nullptr,
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nullptr,
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nullptr,
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is_ncdhw,
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nullptr,
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nullptr,
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xpu::Activation_t::LINEAR,
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nullptr);
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PADDLE_ENFORCE_XDNN_SUCCESS(ret, "conv3d_fusion");
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#else
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int r = xpu::conv3d<XPUType, XPUType, XPUType, int>(dev_ctx.x_context(),
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input_data,
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filter_data_ptr,
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output_data,
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batch_size,
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img_c,
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img_d,
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img_h,
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img_w,
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f,
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ksize,
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strides,
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paddings,
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dilations,
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groups,
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nullptr,
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nullptr,
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nullptr,
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is_ncdhw);
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PADDLE_ENFORCE_XDNN_SUCCESS(r, "conv3d");
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#endif
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});
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}
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} // namespace phi
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PD_REGISTER_KERNEL(conv2d,
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XPU,
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ALL_LAYOUT,
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phi::ConvKernel,
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float,
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#ifdef PADDLE_WITH_XPU_XRE5
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phi::bfloat16,
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#endif
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phi::float16) {
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}
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PD_REGISTER_KERNEL(depthwise_conv2d,
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XPU,
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ALL_LAYOUT,
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phi::DepthwiseConvKernel,
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float,
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phi::float16) {}
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PD_REGISTER_KERNEL(conv3d,
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XPU,
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ALL_LAYOUT,
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phi::Conv3DKernel,
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float,
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#ifdef PADDLE_WITH_XPU_XRE5
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phi::bfloat16,
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#endif
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phi::float16) {
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}
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