wehub-resource-sync
202 lines
8.4 KiB
Plaintext
202 lines
8.4 KiB
Plaintext
// Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "paddle/phi/kernels/roi_pool_grad_kernel.h"
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#include "paddle/phi/backends/gpu/cuda/cuda_graph_with_memory_pool.h"
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#include "paddle/phi/backends/gpu/gpu_context.h"
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#include "paddle/phi/backends/gpu/gpu_launch_config.h"
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#include "paddle/phi/backends/gpu/gpu_primitives.h"
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#include "paddle/phi/common/memory_utils.h"
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#include "paddle/phi/common/place.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/kernels/full_kernel.h"
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#include "paddle/phi/kernels/funcs/math_function.h"
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namespace phi {
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static constexpr int kNumCUDAThreads = 512;
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static constexpr int kNumMaximumNumBlocks = 4096;
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static inline uint32_t NumBlocks(const int64_t N) {
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return static_cast<uint32_t>(
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std::min((N + kNumCUDAThreads - 1) / kNumCUDAThreads,
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static_cast<int64_t>(kNumMaximumNumBlocks)));
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}
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template <typename T, typename IndexType>
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__global__ void GPURoiPoolBackward(const IndexType nthreads,
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const T* input_rois,
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const T* output_grad,
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const int64_t* arg_max_data,
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const IndexType num_rois,
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const float spatial_scale,
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const IndexType channels,
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const IndexType height,
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const IndexType width,
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const int pooled_height,
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const int pooled_width,
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int* box_batch_id_data,
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T* input_grad) {
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IndexType index =
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static_cast<IndexType>(blockIdx.x) * static_cast<IndexType>(blockDim.x) +
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static_cast<IndexType>(threadIdx.x);
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IndexType offset =
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static_cast<IndexType>(blockDim.x) * static_cast<IndexType>(gridDim.x);
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for (IndexType i = index; i < nthreads; i += offset) {
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IndexType pw = i % pooled_width;
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IndexType ph = (i / pooled_width) % pooled_height;
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IndexType c = (i / pooled_width / pooled_height) % channels;
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IndexType n = i / pooled_width / pooled_height / channels;
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int roi_batch_ind = box_batch_id_data[n];
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IndexType input_offset = (roi_batch_ind * channels + c) * height * width;
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IndexType output_offset = (n * channels + c) * pooled_height * pooled_width;
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const T* offset_output_grad = output_grad + output_offset;
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T* offset_input_grad = input_grad + input_offset;
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const int64_t* offset_arg_max_data = arg_max_data + output_offset;
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int64_t arg_max = offset_arg_max_data[ph * pooled_width + pw];
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if (arg_max != -1) {
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CudaAtomicAdd(offset_input_grad + arg_max,
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static_cast<T>(offset_output_grad[ph * pooled_width + pw]));
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}
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}
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}
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template <typename T, typename Context>
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void RoiPoolGradKernel(const Context& dev_ctx,
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const DenseTensor& x,
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const DenseTensor& boxes,
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const optional<DenseTensor>& boxes_num,
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const DenseTensor& arg_max,
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const DenseTensor& out_grad,
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int pooled_height,
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int pooled_width,
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float spatial_scale,
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DenseTensor* dx) {
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auto x_dims = x.dims();
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int64_t channels = x_dims[1];
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int64_t height = x_dims[2];
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int64_t width = x_dims[3];
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int64_t rois_num = boxes.dims()[0];
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if (x.numel() == 0 || boxes.numel() == 0) {
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Full<T, Context>(dev_ctx, dx->dims(), 0, dx);
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return;
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}
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if (dx) {
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DenseTensor box_batch_id_list;
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box_batch_id_list.Resize({rois_num});
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int* box_batch_id_data =
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dev_ctx.template HostAlloc<int>(&box_batch_id_list);
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auto gplace = dev_ctx.GetPlace();
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if (boxes_num) {
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int64_t boxes_batch_size = boxes_num->numel();
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// TODO(large-tensor): downstream functors may still use int; guard until
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// upgraded.
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std::vector<int> boxes_num_list(boxes_batch_size);
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memory_utils::Copy(CPUPlace(),
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boxes_num_list.data(),
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gplace,
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boxes_num->data<int>(),
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sizeof(int) * boxes_batch_size,
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0);
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int start = 0;
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for (int n = 0; n < boxes_batch_size; ++n) {
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for (int i = start; i < start + boxes_num_list[n]; ++i) {
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box_batch_id_data[i] = n;
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}
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start += boxes_num_list[n];
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}
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} else {
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auto boxes_lod = boxes.lod().back();
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int boxes_batch_size = boxes_lod.size() - 1;
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for (int n = 0; n < boxes_batch_size; ++n) {
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for (size_t i = boxes_lod[n]; i < boxes_lod[n + 1]; ++i) {
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box_batch_id_data[i] = n;
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}
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}
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}
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int bytes = box_batch_id_list.numel() * sizeof(int);
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auto roi_ptr = memory_utils::Alloc(
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dev_ctx.GetPlace(),
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bytes,
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Stream(reinterpret_cast<StreamId>(dev_ctx.stream())));
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int* roi_id_data = reinterpret_cast<int*>(roi_ptr->ptr());
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const int* stable_box_batch_id =
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backends::gpu::RestoreHostMemIfCapturingCUDAGraph(
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box_batch_id_data, static_cast<size_t>(bytes / sizeof(int)));
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memory_utils::Copy(gplace,
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roi_id_data,
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CPUPlace(),
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stable_box_batch_id,
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bytes,
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dev_ctx.stream());
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dev_ctx.template Alloc<T>(dx);
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funcs::SetConstant<Context, T> set_zero;
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set_zero(dev_ctx, dx, static_cast<T>(0));
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int64_t output_grad_size = out_grad.numel();
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uint32_t blocks = NumBlocks(output_grad_size);
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uint32_t threads = kNumCUDAThreads;
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if (output_grad_size > 0) {
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if (output_grad_size > std::numeric_limits<int32_t>::max() ||
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dx->numel() > std::numeric_limits<int32_t>::max()) {
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GPURoiPoolBackward<T, int64_t>
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<<<blocks, threads, 0, dev_ctx.stream()>>>(output_grad_size,
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boxes.data<T>(),
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out_grad.data<T>(),
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arg_max.data<int64_t>(),
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rois_num,
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spatial_scale,
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channels,
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height,
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width,
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pooled_height,
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pooled_width,
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roi_id_data,
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dx->data<T>());
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} else {
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GPURoiPoolBackward<T, int32_t>
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<<<blocks, threads, 0, dev_ctx.stream()>>>(output_grad_size,
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boxes.data<T>(),
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out_grad.data<T>(),
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arg_max.data<int64_t>(),
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rois_num,
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spatial_scale,
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channels,
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height,
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width,
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pooled_height,
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pooled_width,
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roi_id_data,
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dx->data<T>());
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}
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}
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}
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}
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} // namespace phi
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PD_REGISTER_KERNEL(
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roi_pool_grad, GPU, ALL_LAYOUT, phi::RoiPoolGradKernel, float, double) {
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kernel->InputAt(3).SetDataType(phi::DataType::INT64);
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}
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