wehub-resource-sync
207 lines
7.9 KiB
Plaintext
207 lines
7.9 KiB
Plaintext
// Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "paddle/phi/kernels/index_select_grad_kernel.h"
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#include "glog/logging.h"
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#include "paddle/common/enforce.h"
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#include "paddle/common/flags.h"
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#include "paddle/phi/backends/gpu/gpu_info.h"
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#include "paddle/phi/backends/gpu/gpu_launch_config.h"
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#include "paddle/phi/backends/gpu/gpu_primitives.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/core/utils/data_type.h"
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#include "paddle/phi/kernels/full_kernel.h"
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#include "paddle/phi/kernels/funcs/math_function.h"
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COMMON_DECLARE_bool(cudnn_deterministic);
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namespace phi {
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template <typename T, typename IndexT>
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__global__ void index_select_grad_cuda_kernel(const T* output_grad,
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T* input_grad,
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const IndexT* index,
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int64_t N,
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int64_t stride,
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int64_t size,
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int64_t delta,
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int64_t dim_size) {
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CUDA_KERNEL_LOOP_TYPE(idx, N, int64_t) {
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int64_t pre_idx = idx / (stride * size);
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int64_t dim_idx = idx % (stride * size) / stride;
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IndexT src_dim_idx = index[dim_idx];
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if (src_dim_idx < 0) {
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src_dim_idx += dim_size;
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}
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int64_t input_idx =
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idx + (delta * pre_idx + src_dim_idx - dim_idx) * stride;
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CudaAtomicAdd(&input_grad[input_idx], output_grad[idx]);
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}
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}
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template <typename T, typename IndexT>
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__global__ void index_select_grad_deterministic_cuda_kernel(
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const T* output_grad,
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T* input_grad,
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const IndexT* index,
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int64_t index_size,
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int64_t stride,
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int64_t pre_size,
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int64_t input_dim_size) {
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int64_t num_columns = pre_size * stride;
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CUDA_KERNEL_LOOP_TYPE(col_idx, num_columns, int64_t) {
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int64_t pre_idx = col_idx / stride;
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int64_t post_idx = col_idx % stride;
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for (int64_t k = 0; k < index_size; ++k) {
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IndexT src_dim_idx = index[k];
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if (src_dim_idx < 0) {
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src_dim_idx += input_dim_size;
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}
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int64_t out_grad_idx = (pre_idx * index_size + k) * stride + post_idx;
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int64_t in_grad_idx =
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(pre_idx * input_dim_size + src_dim_idx) * stride + post_idx;
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input_grad[in_grad_idx] += output_grad[out_grad_idx];
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}
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}
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}
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template <typename T, typename Context>
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void IndexSelectGradKernel(const Context& dev_ctx,
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const DenseTensor& x,
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const DenseTensor& index,
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const DenseTensor& out_grad,
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int dim,
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DenseTensor* x_grad) {
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if (out_grad.numel() == 0) {
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Full<T, Context>(dev_ctx, x.dims(), 0, x_grad);
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return;
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}
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auto* output_grad_data = out_grad.data<T>();
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auto* in_grad_data = dev_ctx.template Alloc<T>(x_grad);
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auto input_dim = x_grad->dims();
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auto output_dim = out_grad.dims();
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dim = dim >= 0 ? dim : dim + input_dim.size();
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auto stride_dim = common::stride(input_dim);
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int64_t stride = stride_dim[dim];
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int64_t size = output_dim[dim];
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int64_t delta = input_dim[dim] - size;
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const auto& index_type = index.dtype();
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bool index_type_match =
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index_type == DataType::INT64 || index_type == DataType::INT32;
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PADDLE_ENFORCE_EQ(index_type_match,
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true,
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common::errors::InvalidArgument(
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"Input(Index) holds the wrong type, it holds %s, but "
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"desires to be %s or %s",
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index_type,
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DataType::INT32,
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DataType::INT64));
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int64_t numel = x_grad->numel();
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if (numel == 0) {
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return;
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}
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int64_t out_nums = out_grad.numel();
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auto stream = dev_ctx.stream();
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funcs::SetConstant<GPUContext, T> index_select_grad_init;
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index_select_grad_init(dev_ctx, x_grad, static_cast<T>(0));
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if (FLAGS_cudnn_deterministic) {
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int64_t pre_size = out_nums / (size * stride);
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int64_t num_columns = pre_size * stride;
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unsigned int block_dim = PADDLE_CUDA_NUM_THREADS;
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const uint64_t grid_x = (num_columns + block_dim - 1) / block_dim;
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PADDLE_ENFORCE_LE_UINT32_MAX(grid_x, "grid.x");
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dim3 grid_dim = dim3(static_cast<uint32_t>(grid_x));
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backends::gpu::LimitGridDim(dev_ctx, &grid_dim);
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if (index_type == DataType::INT64) {
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const int64_t* index_data = index.data<int64_t>();
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index_select_grad_deterministic_cuda_kernel<T, int64_t>
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<<<grid_dim, block_dim, 0, stream>>>(output_grad_data,
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in_grad_data,
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index_data,
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size,
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stride,
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pre_size,
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input_dim[dim]);
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} else {
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const int* index_data = index.data<int>();
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index_select_grad_deterministic_cuda_kernel<T, int>
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<<<grid_dim, block_dim, 0, stream>>>(output_grad_data,
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in_grad_data,
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index_data,
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size,
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stride,
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pre_size,
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input_dim[dim]);
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}
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} else {
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unsigned int block_dim = PADDLE_CUDA_NUM_THREADS;
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const uint64_t grid_x = (out_nums + block_dim - 1) / block_dim;
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PADDLE_ENFORCE_LE_UINT32_MAX(grid_x, "grid.x");
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dim3 grid_dim = dim3(static_cast<uint32_t>(grid_x));
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backends::gpu::LimitGridDim(dev_ctx, &grid_dim);
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if (index_type == DataType::INT64) {
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const int64_t* index_data = index.data<int64_t>();
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index_select_grad_cuda_kernel<T, int64_t>
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<<<grid_dim, block_dim, 0, stream>>>(output_grad_data,
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in_grad_data,
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index_data,
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out_nums,
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stride,
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size,
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delta,
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input_dim[dim]);
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} else {
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const int* index_data = index.data<int>();
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index_select_grad_cuda_kernel<T, int>
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<<<grid_dim, block_dim, 0, stream>>>(output_grad_data,
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in_grad_data,
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index_data,
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out_nums,
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stride,
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size,
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delta,
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input_dim[dim]);
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}
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}
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}
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} // namespace phi
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PD_REGISTER_KERNEL(index_select_grad,
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GPU,
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ALL_LAYOUT,
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phi::IndexSelectGradKernel,
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float,
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double,
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phi::float16,
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phi::bfloat16,
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phi::complex64,
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phi::complex128,
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int,
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int64_t,
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bool) {}
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