wehub-resource-sync
126 lines
4.4 KiB
Plaintext
126 lines
4.4 KiB
Plaintext
// Copyright (c) 2024 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "paddle/phi/kernels/gpu/cvm_grad_kernel.h"
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#pragma once
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#include "paddle/phi/backends/gpu/gpu_primitives.h"
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#include "paddle/phi/core/kernel_registry.h"
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#include "paddle/phi/core/mixed_vector.h"
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#include "paddle/phi/kernels/funcs/eigen/common.h"
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#include "paddle/phi/kernels/impl/cvm_kernel_impl.h"
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namespace phi {
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template <typename T>
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__global__ void CvmGradComputeKernel(const bool use_cvm,
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const int64_t item_width,
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const T* CVM,
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const T* DY,
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T* DX,
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bool has_lod,
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const size_t* lod,
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size_t lod_size,
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int64_t numel) {
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CUDA_KERNEL_LOOP(i, numel) {
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int offset = i % item_width;
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if (offset <= 1) {
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int cvm_id = i / item_width;
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if (has_lod) {
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int low = 1;
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int high = lod_size - 1;
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while (low < high) {
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int mid = (low + high) / 2;
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if (cvm_id < lod[mid])
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high = mid;
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else
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low = mid + 1;
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}
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cvm_id = low - 1;
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}
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DX[i] = CVM[2 * cvm_id + offset];
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} else {
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if (use_cvm) {
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DX[i] = DY[i];
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} else {
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DX[i] = DY[i / item_width * (item_width - 2) + i % item_width - 2];
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}
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}
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}
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}
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template <typename T, typename Context>
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void CVMGradCUDAKernel(const Context& dev_ctx,
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const DenseTensor& x_in,
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const DenseTensor& cvm_in,
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const DenseTensor& out_grad,
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bool use_cvm,
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DenseTensor* x_grad) {
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auto* dx = x_grad;
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T* dx_data = dev_ctx.template Alloc<T>(dx);
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const DenseTensor* cvm = &cvm_in;
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const T* cvm_data = cvm->data<T>();
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const auto* dOut = &out_grad;
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const T* dout_data = dOut->data<T>();
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auto offset = 2;
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auto batch_size = dx->dims()[0];
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auto dx_numel = dx->numel();
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auto item_size = dx_numel / batch_size;
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// for Input X do not have Lod Information.
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auto stream = dev_ctx.stream();
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if (dx->NumLevels() == 0) {
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CvmGradComputeKernel<<<(dx_numel + PADDLE_CUDA_NUM_THREADS - 1) /
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PADDLE_CUDA_NUM_THREADS,
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PADDLE_CUDA_NUM_THREADS,
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0,
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stream>>>(use_cvm,
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item_size,
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cvm_data,
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dout_data,
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dx_data,
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false,
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NULL,
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0,
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dx_numel);
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} else {
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auto lod = dx->lod()[0];
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PADDLE_ENFORCE_EQ(
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batch_size,
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lod[lod.size() - 1],
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common::errors::PreconditionNotMet(
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"Output(X@GRAD)'s dim[0] must be equal to last element of lod"));
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MixVector<size_t> mixv_lod(&lod);
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CvmGradComputeKernel<<<(dx_numel + PADDLE_CUDA_NUM_THREADS - 1) /
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PADDLE_CUDA_NUM_THREADS,
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PADDLE_CUDA_NUM_THREADS,
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0,
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stream>>>(use_cvm,
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item_size,
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cvm_data,
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dout_data,
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dx_data,
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true,
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mixv_lod.CUDAData(dev_ctx.GetPlace()),
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lod.size(),
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dx_numel);
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}
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}
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} // namespace phi
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PD_REGISTER_KERNEL(
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cvm_grad, GPU, ALL_LAYOUT, phi::CVMGradCUDAKernel, float, double) {}
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