// Copyright (c) 2022 PaddlePaddle Authors. All Rights Reserved. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. #include "paddle/phi/kernels/unpool_grad_kernel.h" #include #include #include "paddle/common/enforce.h" #include "paddle/phi/backends/gpu/gpu_context.h" #include "paddle/phi/core/kernel_registry.h" #include "paddle/phi/kernels/funcs/math_function.h" namespace phi { template __global__ void KernelUnpool2dMaxGrad(const int64_t nthreads, const T* input_data, const IndT* indices_data, const int input_height, const int input_width, const int channels, const T* output_data, const T* output_grad, const int output_height, const int output_width, T* input_grad) { CUDA_KERNEL_LOOP_TYPE(linearIndex, nthreads, int64_t) { int c = (linearIndex / input_width / input_height) % channels; int n = linearIndex / input_width / input_height / channels; output_grad += (n * channels + c) * output_height * output_width; IndT maxind = indices_data[linearIndex]; input_grad[linearIndex] = output_grad[maxind]; } } template __global__ void KernelUnpool3dMaxGrad(const int64_t nthreads, const T* input_data, const IndT* indices_data, const int input_depth, const int input_height, const int input_width, const int channels, const T* output_data, const T* output_grad, const int output_depth, const int output_height, const int output_width, T* input_grad) { CUDA_KERNEL_LOOP_TYPE(linearIndex, nthreads, int64_t) { int c = (linearIndex / input_depth / input_width / input_height) % channels; int n = linearIndex / input_depth / input_width / input_height / channels; output_grad += (n * channels + c) * output_depth * output_height * output_width; IndT maxind = indices_data[linearIndex]; input_grad[linearIndex] = output_grad[maxind]; } } template class Unpool2dMaxGradFunctor { public: void operator()(const Context& dev_ctx, const DenseTensor& input, const DenseTensor& indices, const DenseTensor& output, const DenseTensor& output_grad, DenseTensor* input_grad) { // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t batch_size = input.dims()[0]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t input_height = input.dims()[2]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t input_width = input.dims()[3]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t output_channels = output.dims()[1]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t output_height = output.dims()[2]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t output_width = output.dims()[3]; const T* input_data = input.data(); const IndT* indices_data = indices.data(); const T* output_data = output.data(); const T* output_grad_data = output_grad.data(); T* input_grad_data = dev_ctx.template Alloc(input_grad); // Early return for zero-size input to avoid invalid CUDA kernel launch if (input.numel() == 0) { return; } PADDLE_ENFORCE_LE_INT_MAX(input_height, "input_height"); PADDLE_ENFORCE_LE_INT_MAX(input_width, "input_width"); PADDLE_ENFORCE_LE_INT_MAX(output_channels, "output_channels"); PADDLE_ENFORCE_LE_INT_MAX(output_height, "output_height"); PADDLE_ENFORCE_LE_INT_MAX(output_width, "output_width"); int input_height_int = static_cast(input_height); int input_width_int = static_cast(input_width); int output_channels_int = static_cast(output_channels); int output_height_int = static_cast(output_height); int output_width_int = static_cast(output_width); int threads = 1024; int64_t grid_max = dev_ctx.GetCUDAMaxGridDimSize()[0]; int64_t grid_64 = std::min((input.numel() + threads - 1) / threads, grid_max); PADDLE_ENFORCE_LE_UINT32_MAX(grid_64, "unpool_grad grid.x"); uint32_t grid = static_cast(grid_64); KernelUnpool2dMaxGrad <<>>(input.numel(), input_data, indices_data, input_height_int, input_width_int, output_channels_int, output_data, output_grad_data, output_height_int, output_width_int, input_grad_data); } }; template class Unpool3dMaxGradFunctor { public: void operator()(const Context& dev_ctx, const DenseTensor& input, const DenseTensor& indices, const DenseTensor& output, const DenseTensor& output_grad, DenseTensor* input_grad) { // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t batch_size = input.dims()[0]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t input_depth = input.dims()[2]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t input_height = input.dims()[3]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t input_width = input.dims()[4]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t output_channels = output.dims()[1]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t output_depth = output.dims()[2]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t output_height = output.dims()[3]; // TODO(large-tensor): downstream functors may still use int; guard until // upgraded. int64_t output_width = output.dims()[4]; const T* input_data = input.data(); const IndT* indices_data = indices.data(); const T* output_data = output.data(); const T* output_grad_data = output_grad.data(); T* input_grad_data = dev_ctx.template Alloc(input_grad); // Early return for zero-size input to avoid invalid CUDA kernel launch if (input.numel() == 0) { return; } PADDLE_ENFORCE_LE_INT_MAX(input_depth, "input_depth"); PADDLE_ENFORCE_LE_INT_MAX(input_height, "input_height"); PADDLE_ENFORCE_LE_INT_MAX(input_width, "input_width"); PADDLE_ENFORCE_LE_INT_MAX(output_channels, "output_channels"); PADDLE_ENFORCE_LE_INT_MAX(output_depth, "output_depth"); PADDLE_ENFORCE_LE_INT_MAX(output_height, "output_height"); PADDLE_ENFORCE_LE_INT_MAX(output_width, "output_width"); int input_depth_int = static_cast(input_depth); int input_height_int = static_cast(input_height); int input_width_int = static_cast(input_width); int output_channels_int = static_cast(output_channels); int output_depth_int = static_cast(output_depth); int output_height_int = static_cast(output_height); int output_width_int = static_cast(output_width); int threads = 1024; int64_t grid_max = dev_ctx.GetCUDAMaxGridDimSize()[0]; int64_t grid_64 = std::min((input.numel() + threads - 1) / threads, grid_max); PADDLE_ENFORCE_LE_UINT32_MAX(grid_64, "unpool_grad grid.x"); uint32_t grid = static_cast(grid_64); KernelUnpool3dMaxGrad <<>>(input.numel(), input_data, indices_data, input_depth_int, input_height_int, input_width_int, output_channels_int, output_data, output_grad_data, output_depth_int, output_height_int, output_width_int, input_grad_data); } }; template void UnpoolGradKernel(const Context& dev_ctx, const DenseTensor& x, const DenseTensor& indices, const DenseTensor& out, const DenseTensor& out_grad, const std::vector& ksize, const std::vector& strides, const std::vector& paddings, const IntArray& output_size, const std::string& data_format, DenseTensor* x_grad) { T* input_grad_data = dev_ctx.template Alloc(x_grad); if (x_grad && x_grad->numel() == 0) { return; } const T* output_grad_data = out_grad.data(); funcs::SetConstant zero; zero(dev_ctx, x_grad, static_cast(0)); const auto& indices_type = indices.dtype(); if (indices_type == DataType::INT32) { Unpool2dMaxGradFunctor unpool2d_max_backward; unpool2d_max_backward(dev_ctx, x, indices, out, out_grad, x_grad); } else { Unpool2dMaxGradFunctor unpool2d_max_backward; unpool2d_max_backward(dev_ctx, x, indices, out, out_grad, x_grad); } } template void Unpool3dGradKernel(const Context& dev_ctx, const DenseTensor& x, const DenseTensor& indices, const DenseTensor& out, const DenseTensor& out_grad, const std::vector& ksize, const std::vector& strides, const std::vector& paddings, const std::vector& output_size, const std::string& data_format, DenseTensor* x_grad) { T* input_grad_data = dev_ctx.template Alloc(x_grad); if (x_grad && x_grad->numel() == 0) { return; } const T* output_grad_data = out_grad.data(); funcs::SetConstant zero; zero(dev_ctx, x_grad, static_cast(0)); const auto& indices_type = indices.dtype(); if (indices_type == DataType::INT32) { Unpool3dMaxGradFunctor unpool3d_max_backward; unpool3d_max_backward(dev_ctx, x, indices, out, out_grad, x_grad); } else { Unpool3dMaxGradFunctor unpool3d_max_backward; unpool3d_max_backward(dev_ctx, x, indices, out, out_grad, x_grad); } } } // namespace phi PD_REGISTER_KERNEL(unpool_grad, GPU, ALL_LAYOUT, phi::UnpoolGradKernel, float, double, int64_t) {} PD_REGISTER_KERNEL(unpool3d_grad, GPU, ALL_LAYOUT, phi::Unpool3dGradKernel, float, double, int64_t) {}