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Vectorizing your code using Universal Intrinsics {#tutorial_univ_intrin}
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==================================================================
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@tableofcontents
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@prev_tutorial{tutorial_how_to_use_OpenCV_parallel_for_new}
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| | |
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| -: | :- |
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| Compatibility | OpenCV >= 4.11 |
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Goal
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----
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The goal of this tutorial is to provide a guide to using the @ref core_hal_intrin feature to vectorize your C++ code for a faster runtime.
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We'll briefly look into _SIMD intrinsics_ and how to work with wide _registers_, followed by a tutorial on the basic operations using wide registers.
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Theory
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------
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In this section, we will briefly look into a few concepts to better help understand the functionality.
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### Intrinsics
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Intrinsics are functions which are separately handled by the compiler. These functions are often optimized to perform in the most efficient ways possible and hence run faster than normal implementations. However, since these functions depend on the compiler, it makes it difficult to write portable applications.
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### SIMD
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SIMD stands for **Single Instruction, Multiple Data**. SIMD Intrinsics allow the processor to vectorize calculations. The data is stored in what are known as *registers*. A *register* may be *128-bits*, *256-bits* or *512-bits* wide. Each *register* stores **multiple values** of the **same data type**. The size of the register and the size of each value determines the number of values stored in total.
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Depending on what *Instruction Sets* your CPU supports, you may be able to use the different registers. To learn more, look [here](https://en.wikipedia.org/wiki/Instruction_set_architecture)
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### VLA
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VLA stands for **Vector Length Agnostic** .
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A mechanism where the register width is determined by the hardware at runtime rather than being fixed at compile time.
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This allows a single binary to scale its performance across different CPUs within the same architecture (e.g., RVV or SVE).
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Universal Intrinsics
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--------------------
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OpenCV's universal intrinsics provides an abstraction to SIMD and VLA vectorization methods and allows the user to use intrinsics without the need to write system specific code.
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Supported SIMD/VLA technologies are detailed in @ref core_hal_intrin .
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**We will now introduce the available structures and functions:**
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* Register structures
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* Load and store
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* Mathematical Operations
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* Reduce and Mask
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### Register Structures
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The Universal Intrinsics set implements every register as a structure based on the particular SIMD register.
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All types contain the `nlanes` enumeration which gives the exact number of values that the type can hold. This eliminates the need to hardcode the number of values during implementations.
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@note Each register structure is under the `cv` namespace.
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There are **two types** of registers:
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* **Variable sized registers**: These structures do not have a fixed size and their exact bit length is deduced during compilation, based on the available SIMD capabilities. Consequently, the value of the `nlanes` enum is determined in compile time.
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<br>
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Each structure follows the following convention:
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v_[type of value][size of each value in bits]
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For instance, **v_uint8 holds 8-bit unsigned integers** and **v_float32 holds 32-bit floating point values**. We then declare a register like we would declare any object in C++
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Based on the available SIMD instruction set, a particular register will hold different number of values.
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For example: If your computer supports a maximum of 256bit registers,
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* *v_uint8* will hold 32 8-bit unsigned integers
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* *v_float64* will hold 4 64-bit floats (doubles)
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v_uint8 a; // a is a register supporting uint8(char) data
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int n = a.nlanes; // n holds 32
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Available data type and sizes:
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|Type|Size in bits|
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|-:|:-|
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|uint| 8, 16, 32, 64|
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|int | 8, 16, 32, 64|
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|float | 32, 64|
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* **Constant sized registers**: These structures have a fixed bit size and hold a constant number of values. We need to know what SIMD instruction set is supported by the system and select compatible registers. Use these only if exact bit length is necessary.
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<br>
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Each structure follows the convention:
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v_[type of value][size of each value in bits]x[number of values]
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Suppose we want to store
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* 32-bit(*size in bits*) signed integers in a **128 bit register**. Since the register size is already known, we can find out the *number of data points in register* (*128/32 = 4*):
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v_int32x8 reg1 // holds 8 32-bit signed integers.
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* 64-bit floats in 512 bit register:
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v_float64x8 reg2 // reg2.nlanes = 8
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### Load and Store operations
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Now that we know how registers work, let us look at the functions used for filling these registers with values.
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* **Load**: Load functions allow you to *load* values into a register.
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* *Constructors* - When declaring a register structure, we can either provide a memory address from where the register will pick up contiguous values, or provide the values explicitly as multiple arguments (Explicit multiple arguments is available only for Constant Sized Registers):
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float ptr[32] = {1, 2, 3 ..., 32}; // ptr is a pointer to a contiguous memory block of 32 floats
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// Variable Sized Registers //
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int x = v_float32().nlanes; // set x as the number of values the register can hold
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v_float32 reg1(ptr); // reg1 stores first x values according to the maximum register size available.
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v_float32 reg2(ptr + x); // reg stores the next x values
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// Constant Sized Registers //
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v_float32x4 reg1(ptr); // reg1 stores the first 4 floats (1, 2, 3, 4)
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v_float32x4 reg2(ptr + 4); // reg2 stores the next 4 floats (5, 6, 7, 8)
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// Or we can explicitly write down the values.
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v_float32x4(1, 2, 3, 4);
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<br>
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* *Load Function* - We can use the load method and provide the memory address of the data:
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float ptr[32] = {1, 2, 3, ..., 32};
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v_float32 reg_var;
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reg_var = vx_load(ptr); // loads values from ptr[0] upto ptr[reg_var.nlanes - 1]
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v_float32x4 reg_128;
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reg_128 = v_load(ptr); // loads values from ptr[0] upto ptr[3]
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v_float32x8 reg_256;
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reg_256 = v256_load(ptr); // loads values from ptr[0] upto ptr[7]
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v_float32x16 reg_512;
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reg_512 = v512_load(ptr); // loads values from ptr[0] upto ptr[15]
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@note The load function assumes data is unaligned. If your data is aligned, you may use the `vx_load_aligned()` function.
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<br>
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* **Store**: Store functions allow you to *store* the values from a register into a particular memory location.
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* To store values from a register into a memory location, you may use the *v_store()* function:
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float ptr[4];
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v_store(ptr, reg); // store the first 128 bits(interpreted as 4x32-bit floats) of reg into ptr.
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<br>
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@note Ensure **ptr** has the same type as register. You can also cast the register into the proper type before carrying out operations. Simply typecasting the pointer to a particular type will lead wrong interpretation of data.
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### Binary and Unary Operators
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The universal intrinsics set provides element wise binary and unary operations.
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@note Since OpenCV 4.11, C++ operator overloading (e.g., +, ) in Universal Intrinsics has been deprecated in favor of explicit wrapper functions (e.g., v_add, v_mul) to ensure compatibility with VLA architectures.
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See also: https://github.com/opencv/opencv/issues/27267
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* **Arithmetics**: We can add, subtract, multiply and divide two registers element-wise. The registers must be of the same width and hold the same type. To multiply two registers, for example:
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v_float32 a, b; // {a1, ..., an}, {b1, ..., bn}
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v_float32 c = v_add(a, b); // {a1 + b1, ..., an + bn}
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v_flaot32 d = v_mul(a, b); // {a1 * b1, ..., an * bn}
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<br>
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* **Bitwise Logic and Shifts**: We can left shift or right shift the bits of each element of the register. We can also apply bitwise and, or, xor and not operators between two registers element-wise:
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v_int32 as; // {a1, ..., an}
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v_int32 al = v_shl(as, 2); // {a1 << 2, ..., an << 2}
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v_int32 bl = v_shr(as, 2); // {a1 >> 2, ..., an >> 2}
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v_int32 a, b;
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v_int32 a_and_b = v_and(a, b); // {a1 & b1, ..., an & bn}
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<br>
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* **Comparison Operators**: We can compare values between two registers using the v_lt(<), v_gt(>), v_le(<=) , v_ge(>=), v_eq(==) and v_ne(!=). Since each register contains multiple values, we don't get a single bool for these operations. Instead, for true values, all bits are converted to one (0xff for 8 bits, 0xffff for 16 bits, etc), while false values return bits converted to zero.
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// let us consider the following code is run in a 128-bit register
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v_uint8 a; // a = {0, 1, 2, ..., 13, 14, 15}
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v_uint8 b; // b = {15, 14, 13, ..., 2, 1, 0}
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v_uint8 c = v_lt(a, b); // c = {255, 255, 255, ..., 0, 0, 0}
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/*
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let us look at the first 4 values in binary
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a = |00000000|00000001|00000010|00000011|
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b = |00001111|00001110|00001101|00001100|
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c = |11111111|11111111|11111111|11111111|
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If we store the values of c and print them as integers, we will get 255 for true values and 0 for false values.
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*/
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---
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// In a computer supporting 256-bit registers
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v_int32 a; // a = {1, 2, 3, 4, 5, 6, 7, 8}
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v_int32 b; // b = {8, 7, 6, 5, 4, 3, 2, 1}
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v_int32 c = v_lt(a, b); // c = {-1, -1, -1, -1, 0, 0, 0, 0}
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/*
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The true values are 0xffffffff, which in signed 32-bit integer representation is equal to -1.
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*/
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<br>
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* **Min/Max operations**: We can use the *v_min()* and *v_max()* functions to return registers containing element-wise min, or max, of the two registers:
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v_int32 a; // {a1, ..., an}
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v_int32 b; // {b1, ..., bn}
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v_int32 mn = v_min(a, b); // {min(a1, b1), ..., min(an, bn)}
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v_int32 mx = v_max(a, b); // {max(a1, b1), ..., max(an, bn)}
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<br>
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@note Comparison and Min/Max operators are not available for 64 bit integers. Bitwise shift and logic operators are available only for integer values. Bitwise shift is available only for 16, 32 and 64 bit registers.
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### Reduce and Mask
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* **Reduce Operations**: The *v_reduce_min()*, *v_reduce_max()* and *v_reduce_sum()* return a single value denoting the min, max or sum of the entire register:
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v_int32 a; // a = {a1, ..., a4}
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int mn = v_reduce_min(a); // mn = min(a1, ..., an)
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int sum = v_reduce_sum(a); // sum = a1 + ... + an
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<br>
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* **Mask Operations**: Mask operations allow us to replicate conditionals in wide registers. These include:
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* *v_check_all()* - Returns a bool, which is true if all the values in the register are less than zero.
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* *v_check_any()* - Returns a bool, which is true if any value in the register is less than zero.
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* *v_select()* - Returns a register, which blends two registers, based on a mask.
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v_uint8 a; // {a1, .., an}
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v_uint8 b; // {b1, ..., bn}
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v_int32x4 mask: // {0xff, 0, 0, 0xff, ..., 0xff, 0}
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v_uint8 Res = v_select(mask, a, b) // {a1, b2, b3, a4, ..., an-1, bn}
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/*
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"Res" will contain the value from "a" if mask is true (all bits set to 1),
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and value from "b" if mask is false (all bits set to 0)
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We can use comparison operators to generate mask and v_select to obtain results based on conditionals.
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It is common to set all values of b to 0. Thus, v_select will give values of "a" or 0 based on the mask.
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*/
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## Demonstration
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In the following section, we will vectorize a simple convolution function for single channel and compare the results to a scalar implementation.
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@note Not all algorithms are improved by manual vectorization. In fact, in certain cases, the compiler may *autovectorize* the code, thus producing faster results for scalar implementations.
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You may learn more about convolution from the previous tutorial. We use the same naive implementation from the previous tutorial and compare it to the vectorized version.
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The full tutorial code is [here](https://github.com/opencv/opencv/tree/4.x/samples/cpp/tutorial_code/core/univ_intrin/univ_intrin.cpp).
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### Vectorizing Convolution
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We will first implement a 1-D convolution and then vectorize it. The 2-D vectorized convolution will perform 1-D convolution across the rows to produce the correct results.
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#### 1-D Convolution: Scalar
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@snippet univ_intrin.cpp convolution-1D-scalar
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1. We first set up variables and make a border on both sides of the src matrix, to take care of edge cases.
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@snippet univ_intrin.cpp convolution-1D-border
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2. For the main loop, we select an index *i* and offset it on both sides along with the kernel, using the k variable. We store the value in *value* and add it to the *dst* matrix.
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@snippet univ_intrin.cpp convolution-1D-scalar-main
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#### 1-D Convolution: Vector
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We will now look at the vectorized version of 1-D convolution.
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@snippet univ_intrin.cpp convolution-1D-vector
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1. In our case, the kernel is a float. Since the kernel's datatype is the largest, we convert src to float32, forming *src_32*. We also make a border like we did for the naive case.
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@snippet univ_intrin.cpp convolution-1D-convert
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2. Now, for each column in the *kernel*, we calculate the scalar product of the value with all *window* vectors of length `step`. We add these values to the already stored values in ans
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@snippet univ_intrin.cpp convolution-1D-main
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* We declare a pointer to the src_32 and kernel and run a loop for each kernel element
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@snippet univ_intrin.cpp convolution-1D-main-h1
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* We load a register with the current kernel element. A window is shifted from *0* to *len - step* and its product with the kernel_wide array is added to the values stored in *ans*. We store the values back into *ans*
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@snippet univ_intrin.cpp convolution-1D-main-h2
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* Since the length might not be divisible by steps, we take care of the remaining values directly. The number of *tail* values will always be less than *step* and will not affect the performance significantly. We store all the values to *ans* which is a float pointer. We can also directly store them in a `Mat` object
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@snippet univ_intrin.cpp convolution-1D-main-h3
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* Here is an iterative example:
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For example:
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kernel: {k1, k2, k3}
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src: ...|a1|a2|a3|a4|...
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iter1:
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for each idx i in (0, len), 'step' idx at a time
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kernel_wide: |k1|k1|k1|k1|
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window: |a0|a1|a2|a3|
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ans: ...| 0| 0| 0| 0|...
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sum = ans + window * kernel_wide
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= |a0 * k1|a1 * k1|a2 * k1|a3 * k1|
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iter2:
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kernel_wide: |k2|k2|k2|k2|
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window: |a1|a2|a3|a4|
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ans: ...|a0 * k1|a1 * k1|a2 * k1|a3 * k1|...
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sum = ans + window * kernel_wide
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= |a0 * k1 + a1 * k2|a1 * k1 + a2 * k2|a2 * k1 + a3 * k2|a3 * k1 + a4 * k2|
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iter3:
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kernel_wide: |k3|k3|k3|k3|
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window: |a2|a3|a4|a5|
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ans: ...|a0 * k1 + a1 * k2|a1 * k1 + a2 * k2|a2 * k1 + a3 * k2|a3 * k1 + a4 * k2|...
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sum = sum + window * kernel_wide
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= |a0*k1 + a1*k2 + a2*k3|a1*k1 + a2*k2 + a3*k3|a2*k1 + a3*k2 + a4*k3|a3*k1 + a4*k2 + a5*k3|
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@note The function parameters also include *row*, *rowk* and *len*. These values are used when using the function as an intermediate step of 2-D convolution
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#### 2-D Convolution
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Suppose our kernel has *ksize* rows. To compute the values for a particular row, we compute the 1-D convolution of the previous *ksize/2* and the next *ksize/2* rows, with the corresponding kernel row. The final values is simply the sum of the individual 1-D convolutions
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@snippet univ_intrin.cpp convolution-2D
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1. We first initialize variables and make a border above and below the *src* matrix. The left and right sides are handled by the 1-D convolution function.
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@snippet univ_intrin.cpp convolution-2D-init
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2. For each row, we calculate the 1-D convolution of the rows above and below it. we then add the values to the *dst* matrix.
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@snippet univ_intrin.cpp convolution-2D-main
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3. We finally convert the *dst* matrix to a *8-bit* `unsigned char` matrix
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@snippet univ_intrin.cpp convolution-2D-conv
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Results
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-------
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In the tutorial, we used a horizontal gradient kernel. We obtain the same output image for both methods.
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Improvement in runtime varies and will depend on the SIMD capabilities available in your CPU.
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