105 lines
3.6 KiB
Plaintext
105 lines
3.6 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "common/kernels/kernel.h"
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#include "reducedMathPlugin.h"
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using namespace nvinfer1::plugin; // for ReducedDivisor
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namespace nvinfer1
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{
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namespace plugin
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{
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template <unsigned nthdsPerCTA>
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__launch_bounds__(nthdsPerCTA)
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__global__ void reorgKernel(
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const float* input, // input tensor of shape (batch, C, H, W)
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const int volume, // note that volumes of input and output tensors are the same
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ReducedDivisor batch,
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ReducedDivisor C,
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ReducedDivisor H,
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ReducedDivisor W,
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ReducedDivisor C_out,
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ReducedDivisor stride,
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float* output) // output tensor of shape (batch, C * stride * stride, H / stride, W / stride)
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{
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/*
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* Reference
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* https://github.com/pjreddie/darknet/blob/f6d861736038da22c9eb0739dca84003c5a5e275/src/blas_kernels.cu#L370
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* https://github.com/pjreddie/darknet/blob/f6d861736038da22c9eb0739dca84003c5a5e275/src/blas.c#L9
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*/
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// outIndex is row-major position of input coordinates
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for (int outIndex = blockIdx.x * nthdsPerCTA + threadIdx.x; outIndex < volume; outIndex += nthdsPerCTA)
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{
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int i = outIndex;
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// calculate output coordinates from outIndex
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int outW, outH, outC;
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W.divmod(i, i, outW);
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H.divmod(i, i, outH);
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C.divmod(i, i, outC);
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int outN = i;
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// calculate input coordinates based on output coordinates
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// offset is [0, 1, ..., stride * stride - 1] = posH * stride + posW
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int offset, inC, posH, posW;
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C_out.divmod(outC, offset, inC);
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stride.divmod(offset, posH, posW);
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int inH = outH * stride.get() + posH;
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int inW = outW * stride.get() + posW;
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int inN = outN;
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// inIndex is row-major position of input coordinates
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int inIndex = inW + W.get() * stride.get() * (inH + H.get() * stride.get() * (inC + C_out.get() * inN));
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output[outIndex] = input[inIndex];
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}
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}
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pluginStatus_t reorgGPU(
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cudaStream_t stream,
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const int batch,
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const int C,
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const int H,
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const int W,
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const int stride,
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const float* input,
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float* output)
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{
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const int BS = 512; // number of threads in one block
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const int volume = batch * C * H * W; // size of input tensor
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const int GS = (volume + BS - 1) / BS; // number of blocks to launch, calculated so global number of threads is >= volume
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ReducedDivisor C_out(C / (stride * stride));
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reorgKernel<BS><<<GS, BS, 0, stream>>>(input, volume, ReducedDivisor(batch), ReducedDivisor(C), ReducedDivisor(H), ReducedDivisor(W), C_out, ReducedDivisor(stride), output);
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return STATUS_SUCCESS;
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}
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pluginStatus_t reorgInference(
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cudaStream_t stream,
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const int batch,
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const int C,
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const int H,
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const int W,
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const int stride,
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const void* input,
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void* output)
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{
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return reorgGPU(stream, batch, C, H, W, stride, (const float*) input, (float*) output);
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}
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} // namespace plugin
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} // namespace nvinfer1
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