152 lines
4.4 KiB
Plaintext
152 lines
4.4 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* ************************************************************************
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* Modified from pytorch_scatter
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* Copyright (c) 2020 Matthias Fey <matthias.fey@tu-dortmund.de>
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* See https://github.com/rusty1s/pytorch_scatter/blob/master/LICENSE for details
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* ************************************************************************
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*/
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#ifndef TRT_SCATTER_ELEMENTS_TENSOR_INFO_H
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#define TRT_SCATTER_ELEMENTS_TENSOR_INFO_H
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#include "common/plugin.h"
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namespace nvinfer1
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{
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namespace plugin
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{
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namespace detail
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{
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static constexpr int32_t kMAX_TENSORINFO_DIMS = 25;
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// CUDA kernel argument that defines tensor layout
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template <typename TScalar, typename TIndex>
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struct TensorInfo
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{
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TensorInfo();
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TensorInfo(const TScalar* p, int32_t dim, TIndex sz[kMAX_TENSORINFO_DIMS], TIndex st[kMAX_TENSORINFO_DIMS]);
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// Contiguous tensors of more than one dimension are collapsed down
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// to one tensor
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__host__ __device__ inline bool isContiguous() const
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{
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return (dims == 1 && strides[0] == 1);
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}
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const TScalar* data;
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TIndex sizes[kMAX_TENSORINFO_DIMS];
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TIndex strides[kMAX_TENSORINFO_DIMS];
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int32_t dims;
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};
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// Creates TensorInfo object from PluginTensorDesc and data address
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template <typename TScalar, typename TIndex>
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TensorInfo<TScalar, TIndex> getTensorInfo(const void* d, PluginTensorDesc const& t)
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{
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TIndex sz[kMAX_TENSORINFO_DIMS];
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TIndex st[kMAX_TENSORINFO_DIMS];
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int32_t dims = t.dims.nbDims;
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for (int32_t i = 0; i < dims; ++i)
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{
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sz[i] = t.dims.d[i];
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}
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for (int32_t i = dims; i < kMAX_TENSORINFO_DIMS; ++i)
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{
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sz[i] = static_cast<TIndex>(0);
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}
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// calculate strides
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st[dims - 1] = 1;
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for (int32_t i = dims - 2; i >= 0; --i)
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{
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st[i] = st[i + 1] * sz[i + 1];
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}
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return TensorInfo<TScalar, TIndex>(reinterpret_cast<const TScalar*>(d), dims, sz, st);
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}
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template <typename TScalar, typename TIndex>
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TensorInfo<TScalar, TIndex>::TensorInfo()
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{
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data = nullptr;
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dims = 0;
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}
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template <typename TScalar, typename TIndex>
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TensorInfo<TScalar, TIndex>::TensorInfo(
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const TScalar* p, int32_t dim, TIndex sz[kMAX_TENSORINFO_DIMS], TIndex st[kMAX_TENSORINFO_DIMS])
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{
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data = p;
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dims = dim;
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for (int32_t i = 0; i < dim; ++i)
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{
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sizes[i] = sz[i];
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strides[i] = st[i];
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}
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}
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// Translate a linear index for the apply to a T* offset;
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// specialized on `Dims` to reduce nvcc compilation time
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template <typename TScalar, typename TIndex, int tDims>
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struct IndexToOffset
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{
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static __host__ __device__ TIndex get(TIndex linearId, const TensorInfo<TScalar, TIndex>& info)
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{
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TIndex offset = 0;
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// Uses static dims
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for (int32_t i = tDims - 1; i > 0; --i)
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{
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TIndex curDimIndex = linearId % info.sizes[i];
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TIndex curDimOffset = curDimIndex * info.strides[i];
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offset += curDimOffset;
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linearId /= info.sizes[i];
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}
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return offset + linearId * info.strides[0];
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}
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};
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// Uses dynamic (runtime) instead of static (compiletime) dims
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template <typename TScalar, typename TIndex>
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struct IndexToOffset<TScalar, TIndex, -1>
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{
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static inline __host__ __device__ TIndex get(TIndex linearId, const TensorInfo<TScalar, TIndex>& info)
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{
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TIndex offset = 0;
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for (int32_t i = info.dims - 1; i > 0; --i)
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{
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TIndex curDimIndex = linearId % info.sizes[i];
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TIndex curDimOffset = curDimIndex * info.strides[i];
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offset += curDimOffset;
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linearId /= info.sizes[i];
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}
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return offset + linearId * info.strides[0];
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}
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};
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} // namespace detail
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} // namespace plugin
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} // namespace nvinfer1
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#endif // TRT_SCATTER_ELEMENTS_TENSOR_INFO_H
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