wehub-resource-sync
43 lines
2.3 KiB
XML
43 lines
2.3 KiB
XML
<?xml version="1.0" ?>
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<root date="2026-01-01">
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<extension name="BASE">
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<instruction asm="ADD" category="BINARY" extension="BASE" iclass="ADD" iform="ADD_GPRv_GPRv" isa-set="I86" opcode="01" string="ADD (R32, R32)" summary="Add">
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<operand idx="1" name="REG0" r="1" type="reg" w="1" width="32" xtype="int">EAX,ECX,EDX,EBX</operand>
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<operand idx="2" name="REG1" r="1" type="reg" width="32" xtype="int">EAX,ECX,EDX,EBX</operand>
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<operand flag_CF="w" flag_OF="w" idx="3" name="REG2" suppressed="1" type="flags" w="1"/>
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<architecture name="ADL-P">
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<IACA version="3.0" TP="0.30" uops="1" ports="1*IGNORED"/>
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<measurement TP_unrolled="0.25" TP_loop="0.25" uops="1" ports="1*p0156">
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<latency start_op="1" target_op="1" cycles="1"/>
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<latency start_op="2" target_op="1" cycles="1"/>
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</measurement>
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</architecture>
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<architecture name="ZEN5">
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<measurement TP_loop="0.20" uops="1" ports="1*FPADD">
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<latency start_op="1" target_op="1" cycles="1"/>
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</measurement>
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</architecture>
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</instruction>
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<instruction asm="ADD" category="BINARY" extension="BASE" iclass="ADD" iform="ADD_MEMv_GPRv" isa-set="I86" opcode="01" string="ADD (M32, R32)" summary="Add">
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<operand idx="1" memory-prefix="dword ptr" name="MEM0" r="1" type="mem" w="1" width="32"/>
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<operand idx="2" name="REG0" r="1" type="reg" width="32" xtype="int">EAX,ECX,EDX,EBX</operand>
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<architecture name="ADL-P">
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<measurement TP_loop="1.00" uops="2" ports="1*p0156+1*p23+1*p49+1*p78">
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<latency start_op="1" target_op="1" cycles="6"/>
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</measurement>
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</architecture>
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</instruction>
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</extension>
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<extension name="SSE4">
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<instruction asm="CRC32" category="STTNI" extension="SSE4" iclass="CRC32" iform="CRC32_GPR32_GPR8" isa-set="SSE4" opcode="0F38F0" string="CRC32 (R32, R8)" summary="Accumulate CRC32 Value">
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<operand idx="1" name="REG0" r="1" type="reg" w="1" width="32" xtype="int">EAX,ECX,EDX,EBX</operand>
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<operand idx="2" name="REG1" r="1" type="reg" width="8" xtype="int">AL,CL,DL,BL</operand>
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<architecture name="ADL-P">
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<measurement TP_loop="1.00" uops="1" ports="1*p1">
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<latency start_op="1" target_op="1" cycles="3"/>
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</measurement>
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</architecture>
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</instruction>
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</extension>
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</root>
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