wehub-resource-sync
85 lines
3.1 KiB
Plaintext
85 lines
3.1 KiB
Plaintext
/**
|
|
* ESP32-C2 Linker Script Memory Layout
|
|
* This file describes the memory layout (memory blocks) by virtual memory addresses.
|
|
* This linker script is passed through the C preprocessor to include configuration options.
|
|
* Please use preprocessor features sparingly!
|
|
* Restrict to simple macros with numeric values, and/or #if/#endif blocks.
|
|
*/
|
|
|
|
#include "sdkconfig.h"
|
|
#include "ld.common"
|
|
|
|
/**
|
|
* physical memory is mapped twice to the virtual address (IRAM and DRAM).
|
|
* `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
|
|
*/
|
|
_iram_dram_shared = 1;
|
|
|
|
#define SRAM_IRAM_START 0x4037C000
|
|
#define SRAM_DRAM_START 0x3FCA0000
|
|
#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C2 */
|
|
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START + ICACHE_SIZE)
|
|
#define SRAM_DRAM_END 0x403AEB70 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
|
|
|
|
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
|
|
#define SRAM_DRAM_ORG (SRAM_DRAM_START)
|
|
|
|
#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
|
|
|
|
#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
|
|
|
|
MEMORY
|
|
{
|
|
/**
|
|
* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
|
|
* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
|
|
* are connected to the data port of the CPU and eg allow byte-wise access.
|
|
*/
|
|
|
|
/* IRAM for PRO CPU. */
|
|
iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
|
|
|
|
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
|
/* Flash mapped instruction data */
|
|
iram0_2_seg (RX) : org = 0x42000020, len = 0x400000-0x20
|
|
|
|
/**
|
|
* (0x20 offset above is a convenience for the app binary image generation.
|
|
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
|
|
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
|
|
* header. Setting this offset makes it simple to meet the flash cache MMU's
|
|
* constraint that (paddr % 64KB == vaddr % 64KB).)
|
|
*/
|
|
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
|
|
|
/**
|
|
* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
|
|
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
|
|
*/
|
|
dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
|
|
|
|
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
|
/* Flash mapped constant data */
|
|
drom0_0_seg (R) : org = 0x3C000020, len = 0x400000-0x20
|
|
|
|
/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
|
|
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
|
|
|
}
|
|
|
|
/* Heap ends at top of dram0_0_seg */
|
|
_heap_end = 0x40000000;
|
|
|
|
REGION_ALIAS("iram_text_seg", iram0_0_seg);
|
|
REGION_ALIAS("dram_seg", dram0_0_seg);
|
|
|
|
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
|
REGION_ALIAS("flash_text_seg", iram0_2_seg);
|
|
REGION_ALIAS("flash_rodata_seg", drom0_0_seg);
|
|
#else
|
|
REGION_ALIAS("flash_text_seg", iram0_0_seg);
|
|
REGION_ALIAS("flash_rodata_seg", dram0_0_seg);
|
|
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
|
|
|
|
ALIGN_VECTOR_TABLE = 0x100;
|