wehub-resource-sync
523 lines
16 KiB
C
523 lines
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include "esp_err.h"
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#include "soc/soc_caps.h"
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#if SOC_APM_SUPPORTED
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#include "hal/apm_ll.h"
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#include "hal/apm_types.h"
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#if SOC_APM_CTRL_FILTER_SUPPORTED
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/**
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* @brief Helper macro to create a region entry configuration
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*
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*/
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#define APM_HAL_REGION_ENTRY_BASE(PATH,NUM, START, END, PMS) \
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.path_id = (PATH), \
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.regn_num = (NUM), \
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.regn_start_addr = ((START) & ~0x03U), \
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.regn_end_addr = (((END) - 1U) & ~0x03U), \
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.regn_pms = (PMS), \
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.filter_en = true
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#if SOC_APM_SUPPORT_CTRL_CFG_LOCK
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#define APM_HAL_REGION_ENTRY(PATH, NUM, START, END, PMS, LOCK) \
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{ APM_HAL_REGION_ENTRY_BASE(PATH, NUM, START, END, PMS), .lock_en = LOCK }
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#else
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#define APM_HAL_REGION_ENTRY(PATH, NUM, START, END, PMS) \
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{ APM_HAL_REGION_ENTRY_BASE(PATH, NUM, START, END, PMS) }
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#endif
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/**
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* @brief Helper macro to create a security mode configuration
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*
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*/
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#define APM_HAL_SEC_MODE_CFG(CTRL_MOD, MODE, REGNS) \
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{ \
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.ctrl_mod = (CTRL_MOD), \
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.mode = (MODE), \
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.regn_count = sizeof(REGNS) / sizeof((REGNS)[0]), \
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.regions = (REGNS), \
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}
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/**
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* @brief APM controller info structure
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*/
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typedef struct {
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apm_ctrl_module_t ctrl_mod; /*!< APM controller module */
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apm_ctrl_access_path_t path; /*!< Access path */
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} apm_hal_ctrl_info_t;
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/**
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* @brief APM region configuration structure
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*/
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typedef struct {
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apm_ctrl_access_path_t path_id; /*!< Path identifier */
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uint32_t regn_num; /*!< Region number */
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uint32_t regn_start_addr; /*!< Region start address */
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uint32_t regn_end_addr; /*!< Region end address */
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uint32_t regn_pms; /*!< Region permissions */
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bool filter_en; /*!< Filter enable flag */
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#if SOC_APM_SUPPORT_CTRL_CFG_LOCK
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bool lock_en; /*!< Lock enable flag */
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#endif
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} apm_hal_ctrl_region_cfg_t;
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/**
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* @brief APM security mode configuration structure
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*/
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typedef struct {
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apm_ctrl_module_t ctrl_mod; /*!< APM controller module */
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apm_security_mode_t mode; /*!< Security mode */
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uint32_t regn_count; /*!< Number of regions */
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apm_hal_ctrl_region_cfg_t *regions; /*!< Array of region configurations */
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} apm_hal_ctrl_sec_mode_cfg_t;
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/**
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* @brief Set security mode for specified masters
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*
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* @param master_mask Mask of masters to configure
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* @param mode Security mode to set
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*/
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void apm_hal_set_master_sec_mode(uint32_t master_mask, apm_security_mode_t mode);
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/**
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* @brief Set security mode for all masters
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*
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* @param mode Security mode to set
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*/
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void apm_hal_set_master_sec_mode_all(apm_security_mode_t mode);
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#if SOC_APM_SUPPORT_CTRL_CFG_LOCK
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/**
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* @brief Lock security mode for specified masters
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*
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* @param master_mask Mask of masters to configure
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*/
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void apm_hal_lock_master_sec_mode(uint32_t master_mask);
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/**
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* @brief Lock security mode for all masters
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*
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*/
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void apm_hal_lock_master_sec_mode_all(void);
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#endif
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#if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL
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/**
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* @brief Set access permissions for the specified peripherals in the given TEE ctrl module
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*
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* @param ctrl_mod TEE ctrl module
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* @param periph_mask Peripheral mask
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* @param mode Security mode
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* @param pms Access permissions
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*/
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void apm_hal_tee_set_peri_access(apm_tee_ctrl_module_t ctrl_mod, uint64_t periph_mask, apm_security_mode_t mode, apm_perm_t pms);
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/**
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* @brief Set access permissions for all peripherals in the given TEE ctrl module
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*
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* @param ctrl_mod TEE ctrl module
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* @param mode Security mode
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* @param pms Access permissions
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*/
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void apm_hal_tee_set_peri_access_all(apm_tee_ctrl_module_t ctrl_mod, apm_security_mode_t mode, apm_perm_t pms);
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#endif
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/**
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* @brief Enable/disable TEE clock gating for a APM controller module
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*
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* @param ctrl_mod TEE controller module
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* @param enable True to enable, false to disable
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*/
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void apm_hal_tee_enable_clk_gating(apm_tee_ctrl_module_t ctrl_mod, bool enable);
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/**
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* @brief Enable/disable controller filter for specific path
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*
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* @param ctrl_mod APM controller module
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* @param path Access path
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* @param enable True to enable, false to disable
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*/
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void apm_hal_enable_ctrl_filter(apm_ctrl_module_t ctrl_mod, apm_ctrl_access_path_t path, bool enable);
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/**
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* @brief Enable/disable all controller filters
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*
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* @param enable True to enable, false to disable
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*/
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void apm_hal_enable_ctrl_filter_all(bool enable);
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/**
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* @brief Enable/disable region filter
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*
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* @param ctrl_mod APM controller module
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* @param regn_num Region number
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* @param enable True to enable, false to disable
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*/
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void apm_hal_enable_region_filter(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, bool enable);
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/**
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* @brief Set the start address for the given region
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*
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* @param ctrl_mod APM controller module
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* @param regn_num Region number
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* @param addr Address
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*/
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void apm_hal_set_region_start_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr);
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/**
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* @brief Set the end address for the given region
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*
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* @param ctrl_mod APM controller module
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* @param regn_num Region number
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* @param addr Address
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*/
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void apm_hal_set_region_end_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr);
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/**
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* @brief Set the permissions for the specified security mode for the given region
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*
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* @param ctrl_mod APM controller module
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* @param regn_num Region number
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* @param mode Security mode
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*/
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void apm_hal_set_sec_mode_region_attr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms);
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/**
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* @brief Set region filter configuration
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*
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* @param ctrl_mod APM controller module
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* @param mode Security mode
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* @param regn_cfg Region configuration
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*/
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void apm_hal_set_region_filter_cfg(apm_ctrl_module_t ctrl_mod, apm_security_mode_t mode, const apm_hal_ctrl_region_cfg_t *regn_cfg);
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#if SOC_APM_SUPPORT_CTRL_CFG_LOCK
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/**
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* @brief Lock region filter configuration
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*
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* @param ctrl_mod APM controller module
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* @param regn_num Region number
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*/
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void apm_hal_lock_region_filter_cfg(apm_ctrl_module_t ctrl_mod, uint32_t regn_num);
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#endif
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/**
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* @brief Set controller security mode configuration
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*
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* @param cfg Security mode configuration
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*/
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void apm_hal_set_ctrl_sec_mode_cfg(const apm_hal_ctrl_sec_mode_cfg_t *cfg);
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/**
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* @brief Get exception type
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*
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* @param ctrl_info Controller information
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* @return Exception type
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*/
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uint32_t apm_hal_get_exception_type(apm_hal_ctrl_info_t *ctrl_info);
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/**
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* @brief Clear exception status
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*
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* @param ctrl_info Controller information
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*/
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void apm_hal_clear_exception_status(apm_hal_ctrl_info_t *ctrl_info);
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/**
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* @brief Get exception information
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*
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* @param ctrl_info Controller information
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* @param excp_info Exception information structure to fill
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*/
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void apm_hal_get_exception_info(apm_hal_ctrl_info_t *ctrl_info, apm_ctrl_exception_info_t *excp_info);
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/**
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* @brief Enable/disable interrupt
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*
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* @param ctrl_info Controller information
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* @param enable True to enable, false to disable
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*/
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void apm_hal_enable_intr(apm_hal_ctrl_info_t *ctrl_info, bool enable);
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/**
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* @brief Get interrupt source number
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*
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* @param ctrl_info Controller information
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* @return Interrupt source number
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*/
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int apm_hal_get_intr_src_num(apm_hal_ctrl_info_t *ctrl_info);
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/**
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* @brief Enable/disable reset event bypass
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*
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* @param enable True to enable, false to disable
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*/
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void apm_hal_enable_reset_event_bypass(bool enable);
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/**
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* @brief Enable/disable controller clock gating
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*
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* @param ctrl_mod APM controller module
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* @param enable True to enable, false to disable
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*/
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void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable);
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#else
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/**
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* @brief HP_PERI_PMS permission configuration structure
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*/
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typedef struct {
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uint32_t cpu_peri; /*!< Bitmask for CPU_PERIPH slaves */
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uint32_t hp_peri0; /*!< Bitmask for HP_PERIPH0 slaves */
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uint64_t hp_peri1; /*!< Bitmask for HP_PERIPH1 slaves */
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} apm_hal_pms_hp_peri_cfg_t;
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/**
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* @brief PMS region configuration structure
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*/
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typedef struct {
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uint32_t regn_num; /*!< Region number */
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uint32_t regn_start_addr; /*!< Region start address */
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uint32_t regn_end_addr; /*!< Region end address */
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} apm_hal_pms_regn_cfg_t;
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/**
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* @brief PMS master configuration structure
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*/
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typedef struct {
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union {
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struct {
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apm_master_dma_id_t id; /*!< DMA master ID */
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uint32_t regn_pms_rd; /*!< Bitmask of regions the master is permitted to read */
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uint32_t regn_pms_wr; /*!< Bitmask of regions the master is permitted to write */
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} dma;
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struct {
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apm_master_id_t id; /*!< Master ID */
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apm_security_mode_t mode; /*!< Security mode */
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uint32_t regn_pms; /*!< Bitmask of regions the master is permitted to access */
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} lp_peri;
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};
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} apm_hal_pms_master_cfg_t;
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/**
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* @brief Helper macro to create a PMS region entry configuration
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*/
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#define APM_HAL_PMS_REGION_ENTRY(NUM, START, END) \
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{ \
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.regn_num = (NUM), \
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.regn_start_addr = (START), \
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.regn_end_addr = (END), \
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}
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/**
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* @brief Helper macro to create a DMA_PMS master entry configuration
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*/
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#define APM_HAL_DMA_PMS_MASTER_ENTRY(ID, R_PMS, W_PMS) \
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{ \
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.dma = { \
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.id = (ID), \
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.regn_pms_rd = (R_PMS), \
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.regn_pms_wr = (W_PMS), \
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}, \
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}
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/**
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* @brief Helper macro to create an LP_PERI_PMS master entry configuration
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*/
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#define APM_HAL_LP_PERI_PMS_MASTER_ENTRY(ID, MODE, REGN_PMS) \
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{ \
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.lp_peri = { \
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.id = (ID), \
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.mode = (MODE), \
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.regn_pms = (REGN_PMS), \
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}, \
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}
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/**
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* @brief Set DMA_PMS region address bounds
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*
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* @param regn_num Region number
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* @param start_addr Region start address
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* @param end_addr Region end address
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*/
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void apm_hal_dma_pms_set_region_bounds(uint32_t regn_num, uint32_t start_addr, uint32_t end_addr);
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/**
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* @brief Set DMA_PMS read/write region access mask for a DMA master
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*
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* @param mid DMA master ID
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* @param regn_rd_mask Bitmask of regions the master is permitted to read
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* @param regn_wr_mask Bitmask of regions the master is permitted to write
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*/
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void apm_hal_dma_pms_set_master_region_attr(apm_master_dma_id_t mid, uint32_t regn_rd_mask, uint32_t regn_wr_mask);
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/**
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* @brief Set DMA_PMS region configurations
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*
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* @param regn_count Number of regions to configure
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* @param regn_cfg Array of region configurations
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*/
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void apm_hal_dma_pms_set_region_cfg(uint32_t regn_count, const apm_hal_pms_regn_cfg_t *regn_cfg);
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/**
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* @brief Set DMA_PMS master configurations
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*
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* @param master_count Number of masters to configure
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* @param cfg Array of master configurations
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*/
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void apm_hal_dma_pms_set_master_cfg(uint32_t master_count, const apm_hal_pms_master_cfg_t *cfg);
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/**
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* @brief Set HP2LP_PERI_PMS access permissions for HP CPU
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*
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* @param core_id CPU core ID
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* @param mode Security mode
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* @param enable_mask Bitmask of LP peripherals to enable access to
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*/
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void apm_hal_hp2lp_peri_pms_set_hpcpu_access(int core_id, apm_security_mode_t mode, uint32_t enable_mask);
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/**
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* @brief Set LP_PERI_PMS access permissions for LP CPU
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*
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* @param enable_mask Bitmask of LP peripherals to enable access to
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*/
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void apm_hal_lp_peri_pms_set_lpcpu_access(uint32_t enable_mask);
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/**
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* @brief Set HP_PERI PMS access permissions for HP CPU
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*
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* @param core_id CPU core ID
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* @param mode Security mode
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* @param cfg HP peripheral permission configuration
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*/
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void apm_hal_hp_peri_pms_set_hpcpu_access(int core_id, apm_security_mode_t mode, const apm_hal_pms_hp_peri_cfg_t *cfg);
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/**
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* @brief Set LP2HP_PERI PMS access permissions for LP CPU
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*
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* @param cfg HP peripheral permission configuration
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*/
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void apm_hal_lp2hp_peri_pms_set_lpcpu_access(const apm_hal_pms_hp_peri_cfg_t *cfg);
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/**
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* @brief Set LP_PERI_PMS region address bounds
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*
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* @param regn_num Region number
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* @param start_addr Region start address
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* @param end_addr Region end address
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*/
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void apm_hal_lp_peri_pms_set_region_bounds(uint32_t regn_num, uint32_t start_addr, uint32_t end_addr);
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/**
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* @brief Set LP_PERI_PMS region access mask for a master
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*
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* @param mid Master ID
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* @param mode Security mode
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* @param regn_pms_mask Bitmask of regions the master is permitted to access
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*/
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void apm_hal_lp_peri_pms_set_master_region_attr(apm_master_id_t mid, apm_security_mode_t mode, uint32_t regn_pms_mask);
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/**
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* @brief Set LP_PERI_PMS region configurations
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*
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* @param regn_count Number of regions to configure
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* @param regn_cfg Array of region configurations
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*/
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void apm_hal_lp_peri_pms_set_region_cfg(uint32_t regn_count, const apm_hal_pms_regn_cfg_t *regn_cfg);
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/**
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* @brief Set LP_PERI_PMS master configurations
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*
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* @param master_count Number of masters to configure
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* @param master_cfg Array of master configurations
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*/
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void apm_hal_lp_peri_pms_set_master_cfg(uint32_t master_count, const apm_hal_pms_master_cfg_t *master_cfg);
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/**
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* @brief Enable/disable PMS violation interrupt for a controller module
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*
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* @param ctrl_mod APM controller module
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* @param enable True to enable, false to disable
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*/
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void apm_hal_enable_intr(apm_ctrl_module_t ctrl_mod, bool enable);
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/**
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* @brief Clear PMS violation interrupt for a controller module
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*
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* @param ctrl_mod APM controller module
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*/
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void apm_hal_clear_intr(apm_ctrl_module_t ctrl_mod);
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/**
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* @brief Get the combined interrupt status for all PMS controller modules
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*
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* @return Bitmask of modules with a pending interrupt
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*/
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uint32_t apm_hal_get_intr_status(void);
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/**
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* @brief Get PMS violation exception information
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*
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* @param type Exception type identifier
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* @param excp_info Pointer to structure to fill with exception details
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*/
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void apm_hal_get_exception_info(apm_ctrl_exception_type type, apm_ctrl_exception_info_t *excp_info);
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/**
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* @brief Get interrupt source number for a PMS controller module
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*
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* @param ctrl_mod APM controller module
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* @return Interrupt source number
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*/
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int apm_hal_get_intr_src_num(apm_ctrl_module_t ctrl_mod);
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/**
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* @brief Enable/disable clock gating for a PMS controller module
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*
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* @param ctrl_mod APM controller module
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* @param enable True to enable, false to disable
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*/
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void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable);
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#endif // SOC_APM_CTRL_FILTER_SUPPORTED
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#elif SOC_APM_CTRL_FILTER_SUPPORTED // SOC_APM_CTRL_FILTER_SUPPORTED
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#if SOC_IS(ESP32H4)
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#include "soc/hp_apm_reg.h"
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#define apm_hal_enable_ctrl_filter_all(en) \
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REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0);
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#elif SOC_IS(ESP32S31)
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#include "soc/hp_apm_reg.h"
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#include "soc/hp_mem_apm_reg.h"
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#include "soc/lp_apm_reg.h"
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#define apm_hal_enable_ctrl_filter_all(en) \
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REG_WRITE(LP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \
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REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \
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REG_WRITE(HP_MEM_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0);
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#else
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#include "soc/hp_apm_reg.h"
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#include "soc/lp_apm_reg.h"
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#include "soc/lp_apm0_reg.h"
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#define apm_hal_enable_ctrl_filter_all(en) \
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REG_WRITE(LP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \
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REG_WRITE(LP_APM0_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \
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REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0);
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#endif
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#endif //SOC_APM_CTRL_FILTER_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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