wehub-resource-sync
435 lines
14 KiB
C
435 lines
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "hal/config.h"
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#include "soc/dma_pms_reg.h"
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#include "soc/hp2lp_peri_pms_reg.h"
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#include "soc/hp_peri_pms_reg.h"
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#include "soc/lp2hp_peri_pms_reg.h"
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#include "soc/lp_peri_pms_reg.h"
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#include "hal/apm_types.h"
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#include "soc/apm_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Offsets for indexing R/W attribute registers for DMA masters */
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#define APM_LL_DMA_PMS_ATTR_RD_OFFSET 0x04U
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#define APM_LL_DMA_PMS_ATTR_WR_OFFSET_1 0x04U
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#define APM_LL_DMA_PMS_ATTR_WR_OFFSET_2 0x14U
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/* Offsets for indexing HP2LP_PERI_PMS registers by CPU core and security mode */
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#define APM_LL_HP2LP_PERI_PMS_CORE_OFFSET 0x08U
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#define APM_LL_HP2LP_PERI_PMS_MODE_OFFSET 0x04U
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/* Bit-field masks/shifts for extracting LP_PERI_PMS region permission fields */
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#define APM_LL_LP_PERI_PMS_REGN0_1_MASK 0x03U
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#define APM_LL_LP_PERI_PMS_REGN2_7_SHIFT 2U
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#define APM_LL_LP_PERI_PMS_REGN2_7_MASK 0x3FU
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/* Helper macro for indexing HP_PERI_PMS registers by core, mode, and register index */
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#define APM_LL_HP_PERI_PMS_CORE_OFFSET 0x20U
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#define APM_LL_HP_PERI_PMS_MODE_OFFSET 0x10U
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#define APM_LL_HP_PERI_PMS_REG_OFFSET 0x04U
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#define HP_PERI_PMS_COREn_xM_REGk_REG(cid, mode, regk) \
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(PMS_CORE0_MM_HP_PERI_PMS_REG0_REG \
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+ ((cid) * APM_LL_HP_PERI_PMS_CORE_OFFSET) \
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+ ((mode) * APM_LL_HP_PERI_PMS_MODE_OFFSET) \
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+ ((regk) * APM_LL_HP_PERI_PMS_REG_OFFSET))
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/* Helper macros for indexing LP_PERI_PMS configurable region address registers */
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#define APM_LL_LP_PERI_PMS_REGION_OFFSET 0x08U
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#define APM_LL_LP_PERI_PMS_REGION_GAP 0x08U
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#define PMS_PERI_REGION_LOW_REG(regn) \
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(PMS_PERI_REGION0_LOW_REG \
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+ ((regn) * APM_LL_LP_PERI_PMS_REGION_OFFSET) \
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+ (((regn) >= 2U) ? APM_LL_LP_PERI_PMS_REGION_GAP : 0U))
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#define PMS_PERI_REGION_HIGH_REG(regn) \
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(PMS_PERI_REGION0_HIGH_REG \
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+ ((regn) * APM_LL_LP_PERI_PMS_REGION_OFFSET) \
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+ (((regn) >= 2U) ? APM_LL_LP_PERI_PMS_REGION_GAP : 0U))
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/**
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* @brief Enable/disable clock gating for DMA_PMS
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*
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* @param enable True to enable, false to disable
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*/
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static inline void apm_ll_dma_pms_enable_clk_gating(bool enable)
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{
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if (enable) {
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REG_CLR_BIT(PMS_DMA_CLK_EN_REG, PMS_DMA_CLK_EN);
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} else {
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REG_SET_BIT(PMS_DMA_CLK_EN_REG, PMS_DMA_CLK_EN);
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}
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}
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/**
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* @brief Set region start address in DMA_PMS
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*
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* @param regn_num Region number
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* @param addr Start address
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*/
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static inline void apm_ll_dma_pms_set_region_start_addr(uint32_t regn_num, uint32_t addr)
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{
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REG_WRITE(PMS_DMA_REGION0_LOW_REG + APM_DMA_PMS_REGION_ADDR_OFFSET * regn_num, addr);
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}
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/**
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* @brief Set region end address in DMA_PMS
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*
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* @param regn_num Region number
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* @param addr End address
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*/
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static inline void apm_ll_dma_pms_set_region_end_addr(uint32_t regn_num, uint32_t addr)
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{
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REG_WRITE(PMS_DMA_REGION0_HIGH_REG + APM_DMA_PMS_REGION_ADDR_OFFSET * regn_num, addr);
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}
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/**
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* @brief Set read-access region mask for a DMA master in DMA_PMS
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*
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* @param mid DMA master ID
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* @param regn_mask Bitmask of regions the master is permitted to read
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*/
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static inline void apm_ll_dma_pms_set_region_attr_r(apm_master_dma_id_t mid, uint32_t regn_mask)
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{
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uint32_t offs = APM_DMA_PMS_REGION_ATTR_OFFSET * (uint32_t)mid;
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if (mid >= APM_MASTER_DMA_AXI_PDMA_LCDCAM) {
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offs += APM_LL_DMA_PMS_ATTR_RD_OFFSET;
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}
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REG_WRITE(PMS_DMA_GDMA_CH0_R_PMS_REG + offs, regn_mask);
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}
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/**
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* @brief Set write-access region mask for a DMA master in DMA_PMS
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*
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* @param mid DMA master ID
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* @param regn_mask Bitmask of regions the master is permitted to write
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*/
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static inline void apm_ll_dma_pms_set_region_attr_w(apm_master_dma_id_t mid, uint32_t regn_mask)
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{
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uint32_t offs = APM_DMA_PMS_REGION_ATTR_OFFSET * (uint32_t)mid;
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if (mid == APM_MASTER_DMA_AHB_PDMA_RMT) {
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offs += APM_LL_DMA_PMS_ATTR_WR_OFFSET_2;
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} else if (mid >= APM_MASTER_DMA_AXI_PDMA_LCDCAM) {
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offs += APM_LL_DMA_PMS_ATTR_WR_OFFSET_1;
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}
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REG_WRITE(PMS_DMA_GDMA_CH0_W_PMS_REG + offs, regn_mask);
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}
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/**
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* @brief Enable/disable clock gating for HP_PERI_PMS
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*
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* @param enable True to enable, false to disable
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*/
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static inline void apm_ll_hp_peri_pms_enable_clk_gating(bool enable)
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{
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if (enable) {
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REG_CLR_BIT(PMS_HP_PERI_PMS_CLK_EN_REG, PMS_HP_PERI_PMS_CLK_EN);
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} else {
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REG_SET_BIT(PMS_HP_PERI_PMS_CLK_EN_REG, PMS_HP_PERI_PMS_CLK_EN);
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}
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}
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/**
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* @brief Enable/disable HP CPU access to a CPU peripheral in HP_PERI_PMS
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*
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* @param core_id CPU core ID
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* @param mode Security mode
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* @param sid CPU peripheral slave ID
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* @param enable True to enable access, false to disable
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*/
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static inline void apm_ll_hp_peri_pms_enable_hpcpu_cpu_peri_access(const int core_id, apm_security_mode_t mode, apm_slave_cpu_periph_id_t sid, bool enable)
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{
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if (enable) {
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REG_SET_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, 0), BIT(sid));
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} else {
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REG_CLR_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, 0), BIT(sid));
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}
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}
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/**
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* @brief Enable/disable HP CPU access to an HP peripheral (group 0) in HP_PERI_PMS
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*
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* @param core_id CPU core ID
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* @param mode Security mode
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* @param sid HP peripheral group 0 slave ID
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* @param enable True to enable access, false to disable
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*/
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static inline void apm_ll_hp_peri_pms_enable_hpcpu_hp_peri0_access(const int core_id, apm_security_mode_t mode, apm_slave_hp_periph0_id_t sid, bool enable)
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{
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if (enable) {
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REG_SET_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, 1), BIT(sid));
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} else {
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REG_CLR_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, 1), BIT(sid));
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}
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}
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/**
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* @brief Enable/disable HP CPU access to an HP peripheral (group 1) in HP_PERI_PMS
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*
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* @param core_id CPU core ID
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* @param mode Security mode
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* @param sid HP peripheral group 1 slave ID
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* @param enable True to enable access, false to disable
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*/
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static inline void apm_ll_hp_peri_pms_enable_hpcpu_hp_peri1_access(const int core_id, apm_security_mode_t mode, apm_slave_hp_periph1_id_t sid, bool enable)
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{
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uint32_t regk = (sid < 32) ? 2U : 3U;
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if (enable) {
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REG_SET_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, regk), BIT(sid & 0x1FU));
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} else {
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REG_CLR_BIT(HP_PERI_PMS_COREn_xM_REGk_REG(core_id, mode, regk), BIT(sid & 0x1FU));
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}
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}
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/**
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* @brief Enable/disable clock gating for HP2LP_PERI_PMS
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*
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* @param enable True to enable, false to disable
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*/
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static inline void apm_ll_hp2lp_peri_pms_enable_clk_gating(bool enable)
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{
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if (enable) {
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REG_CLR_BIT(PMS_HP2LP_PERI_PMS_CLK_EN_REG, PMS_HP2LP_PERI_PMS_CLK_EN);
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} else {
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REG_SET_BIT(PMS_HP2LP_PERI_PMS_CLK_EN_REG, PMS_HP2LP_PERI_PMS_CLK_EN);
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}
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}
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/**
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* @brief Enable/disable HP CPU access to an LP peripheral in HP2LP_PERI_PMS
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*
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* @param core_id CPU core ID
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* @param mode Security mode
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* @param sid LP peripheral slave ID
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* @param enable True to enable access, false to disable
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*/
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static inline void apm_ll_hp2lp_peri_pms_enable_hpcpu_access(const int core_id, apm_security_mode_t mode, apm_slave_lp_periph_t sid, bool enable)
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{
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uint32_t reg = PMS_HP_CORE0_MM_PMS_REG0_REG
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+ (core_id * APM_LL_HP2LP_PERI_PMS_CORE_OFFSET)
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+ (mode * APM_LL_HP2LP_PERI_PMS_MODE_OFFSET);
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if (enable) {
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REG_SET_BIT(reg, BIT(sid));
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} else {
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REG_CLR_BIT(reg, BIT(sid));
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}
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}
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/**
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* @brief Enable/disable clock gating for LP_PERI_PMS
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*
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* @param enable True to enable, false to disable
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*/
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static inline void apm_ll_lp_peri_pms_enable_clk_gating(bool enable)
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{
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if (enable) {
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REG_CLR_BIT(PMS_LP_PERI_PMS_CLK_EN_REG, PMS_LP_PERI_PMS_CLK_EN);
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} else {
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REG_SET_BIT(PMS_LP_PERI_PMS_CLK_EN_REG, PMS_LP_PERI_PMS_CLK_EN);
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}
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}
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/**
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* @brief Enable/disable LP CPU access to an LP peripheral in LP_PERI_PMS
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*
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* @param sid LP peripheral slave ID
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* @param enable True to enable access, false to disable
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*/
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static inline void apm_ll_lp_peri_pms_enable_lpcpu_access(apm_slave_lp_periph_t sid, bool enable)
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{
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if (enable) {
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REG_SET_BIT(PMS_LP_MM_LP_PERI_PMS_REG0_REG, BIT(sid));
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} else {
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REG_CLR_BIT(PMS_LP_MM_LP_PERI_PMS_REG0_REG, BIT(sid));
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}
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}
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/**
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* @brief Set region start address in LP_PERI_PMS
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*
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* @param regn_num Region number
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* @param addr Start address
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*/
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static inline void apm_ll_lp_peri_pms_set_region_start_addr(uint32_t regn_num, uint32_t addr)
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{
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REG_WRITE(PMS_PERI_REGION_LOW_REG(regn_num), addr);
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}
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/**
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* @brief Set region end address in LP_PERI_PMS
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*
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* @param regn_num Region number
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* @param addr End address
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*/
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static inline void apm_ll_lp_peri_pms_set_region_end_addr(uint32_t regn_num, uint32_t addr)
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{
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REG_WRITE(PMS_PERI_REGION_HIGH_REG(regn_num), addr);
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}
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/**
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* @brief Set LP_PERI_PMS region access permissions for HP CPU core 0
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*
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* @param mode Security mode
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* @param regn_mask Bitmask of regions the core is permitted to access
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*/
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static inline void apm_ll_lp_peri_pms_hpcpu0_set_region_access(apm_security_mode_t mode, uint32_t regn_mask)
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{
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uint32_t regn01 = regn_mask & APM_LL_LP_PERI_PMS_REGN0_1_MASK;
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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uint32_t regn27 = (regn_mask >> APM_LL_LP_PERI_PMS_REGN2_7_SHIFT) & APM_LL_LP_PERI_PMS_REGN2_7_MASK;
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#endif
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switch (mode) {
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case APM_SEC_MODE_TEE:
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/* regions 0–1 */
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REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_MM_REGION_PMS, regn01);
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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/* regions 2–7 */
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REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_HP_CORE0_MM_REGION_2_TO_7_PMS, regn27);
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#endif
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break;
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case APM_SEC_MODE_REE:
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/* regions 0–1 */
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REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_UM_REGION_PMS, regn01);
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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/* regions 2–7 */
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REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_HP_CORE0_UM_REGION_2_TO_7_PMS, regn27);
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#endif
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break;
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default:
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break;
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}
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}
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/**
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* @brief Set LP_PERI_PMS region access permissions for HP CPU core 1
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*
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* @param mode Security mode
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* @param regn_mask Bitmask of regions the core is permitted to access
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*/
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static inline void apm_ll_lp_peri_pms_hpcpu1_set_region_access(apm_security_mode_t mode, uint32_t regn_mask)
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{
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uint32_t regn01 = regn_mask & APM_LL_LP_PERI_PMS_REGN0_1_MASK;
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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uint32_t regn27 = (regn_mask >> APM_LL_LP_PERI_PMS_REGN2_7_SHIFT) & APM_LL_LP_PERI_PMS_REGN2_7_MASK;
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#endif
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switch (mode) {
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case APM_SEC_MODE_TEE:
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/* regions 0–1 */
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REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_MM_REGION_PMS, regn01);
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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/* regions 2–7 */
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REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_HP_CORE1_MM_REGION_2_TO_7_PMS, regn27);
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#endif
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break;
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case APM_SEC_MODE_REE:
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/* regions 0–1 */
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REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_UM_REGION_PMS, regn01);
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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/* regions 2–7 */
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REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_HP_CORE1_UM_REGION_2_TO_7_PMS, regn27);
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#endif
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break;
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default:
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break;
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}
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}
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/**
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* @brief Set LP_PERI_PMS region access permissions for LP CPU
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*
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* @param regn_mask Bitmask of regions the LP CPU is permitted to access
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*/
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static inline void apm_ll_lp_peri_pms_lpcpu_set_region_access(uint32_t regn_mask)
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{
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/* regions 0–1 */
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REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_LP_CORE_REGION_PMS, regn_mask & APM_LL_LP_PERI_PMS_REGN0_1_MASK);
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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/* regions 2–7 */
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REG_SET_FIELD(PMS_PERI_REGION_2_TO_7_PMS_REG, PMS_LP_CORE_REGION_2_TO_7_PMS,
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(regn_mask >> APM_LL_LP_PERI_PMS_REGN2_7_SHIFT) & APM_LL_LP_PERI_PMS_REGN2_7_MASK);
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#endif
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}
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/**
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* @brief Enable/disable clock gating for LP2HP_PERI_PMS
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*
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* @param enable True to enable, false to disable
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*/
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static inline void apm_ll_lp2hp_peri_pms_enable_clk_gating(bool enable)
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{
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if (enable) {
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REG_CLR_BIT(PMS_LP2HP_PERI_PMS_CLK_EN_REG, PMS_LP2HP_PERI_PMS_CLK_EN);
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} else {
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REG_SET_BIT(PMS_LP2HP_PERI_PMS_CLK_EN_REG, PMS_LP2HP_PERI_PMS_CLK_EN);
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}
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}
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/**
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* @brief Enable/disable LP CPU access to a CPU peripheral in LP2HP_PERI_PMS
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*
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* @param sid CPU peripheral slave ID
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* @param enable True to enable access, false to disable
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*/
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static inline void apm_ll_lp2hp_peri_pms_enable_lpcpu_cpu_peri_access(apm_slave_cpu_periph_id_t sid, bool enable)
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{
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if (enable) {
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REG_SET_BIT(PMS_LP_MM_PMS_REG0_REG, BIT(sid));
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} else {
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REG_CLR_BIT(PMS_LP_MM_PMS_REG0_REG, BIT(sid));
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}
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}
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/**
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* @brief Enable/disable LP CPU access to an HP peripheral (group 0) in LP2HP_PERI_PMS
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*
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* @param sid HP peripheral group 0 slave ID
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* @param enable True to enable access, false to disable
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*/
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static inline void apm_ll_lp2hp_peri_pms_enable_lpcpu_hp_peri0_access(apm_slave_hp_periph0_id_t sid, bool enable)
|
||
{
|
||
if (enable) {
|
||
REG_SET_BIT(PMS_LP_MM_PMS_REG1_REG, BIT(sid));
|
||
} else {
|
||
REG_CLR_BIT(PMS_LP_MM_PMS_REG1_REG, BIT(sid));
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @brief Enable/disable LP CPU access to an HP peripheral (group 1) in LP2HP_PERI_PMS
|
||
*
|
||
* @param sid HP peripheral group 1 slave ID
|
||
* @param enable True to enable access, false to disable
|
||
*/
|
||
static inline void apm_ll_lp2hp_peri_pms_enable_lpcpu_hp_peri1_access(apm_slave_hp_periph1_id_t sid, bool enable)
|
||
{
|
||
uint32_t reg = (sid < 32U) ? PMS_LP_MM_PMS_REG2_REG : PMS_LP_MM_PMS_REG3_REG;
|
||
if (enable) {
|
||
REG_SET_BIT(reg, BIT(sid & 0x1FU));
|
||
} else {
|
||
REG_CLR_BIT(reg, BIT(sid & 0x1FU));
|
||
}
|
||
}
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif
|