wehub-resource-sync
237 lines
10 KiB
C++
237 lines
10 KiB
C++
/***************************************************************************************************
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* Copyright (c) 2017 - 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holdvr nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************************************/
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// Copyright (c) Microsoft Corporation.
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// SPDX-License-Identifier: Apache-2.0
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// DeepSpeed Team
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#pragma once
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#include <type_traits>
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#include "cutlass/arch/mma.h"
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template <typename arch, typename scalar_t>
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struct CheckArch {
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static constexpr bool isPreVolta = arch::kMinComputeCapability < 70;
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// DISPATCH_ARCHTAG only binds Sm70/Sm75/Sm80+, so overlap with isPreVolta is unreachable.
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static constexpr bool isPreAmpere = arch::kMinComputeCapability < 80;
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static constexpr bool isAmpere = arch::kMinComputeCapability >= 80;
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static constexpr bool value = (isPreVolta && std::is_same_v<scalar_t, float>) ||
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(isPreAmpere && !std::is_same_v<scalar_t, cutlass::bfloat16_t>) ||
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isAmpere;
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};
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#define DISPATCH_ARCHTAG(CC, func) \
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{ \
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if ((CC) >= 80) { \
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using ArchTag = cutlass::arch::Sm80; \
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func; \
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} else if ((CC) >= 75) { \
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using ArchTag = cutlass::arch::Sm75; \
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func; \
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} else if ((CC) >= 70) { \
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using ArchTag = cutlass::arch::Sm70; \
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func; \
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} else { \
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EVOFORMER_CHECK(false, "Only GPUs with Tensor Core (SM >= 70) are supported"); \
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} \
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}
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#define DISPATCH_TYPES(tensor, func) \
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{ \
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if (tensor.scalar_type() == at::ScalarType::Half) { \
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using scalar_t = cutlass::half_t; \
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using torch_scalar_t = at::Half; \
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func; \
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} else if (tensor.scalar_type() == at::ScalarType::BFloat16) { \
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using scalar_t = cutlass::bfloat16_t; \
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using torch_scalar_t = at::BFloat16; \
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func; \
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} else { \
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EVOFORMER_CHECK(false, "Only fp16 and bf16 supported at the moment"); \
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} \
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}
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#define DISPATCH_BOOL(BOOL_V, BOOL_NAME, F) \
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{ \
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if (BOOL_V) { \
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constexpr bool BOOL_NAME = true; \
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F(); \
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} else { \
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constexpr bool BOOL_NAME = false; \
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F(); \
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} \
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}
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#ifdef TORCH_CHECK
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#define CHECK_ALIGNED_PTR(PTR, ALIGNMENT) \
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EVOFORMER_CHECK(uint64_t(PTR) % ALIGNMENT == 0, #PTR " is not correctly aligned")
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#define EVOFORMER_CHECK TORCH_CHECK
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#elif defined(__CUDACC_RTC__)
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#define CHECK_ALIGNED_PTR(PTR, ALIGNMENT) \
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if (!(uint64_t(PTR) % ALIGNMENT == 0)) { return false; }
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#define EVOFORMER_CHECK(COND, ERR) \
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if (!(COND)) { return false; }
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#else
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#include <iostream>
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#define CHECK_ALIGNED_PTR(PTR, ALIGNMENT) \
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if (!(uint64_t(PTR) % ALIGNMENT == 0)) { \
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std::cerr << #PTR " is not correctly aligned\n"; \
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return false; \
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}
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#define EVOFORMER_CHECK(COND, ERR) \
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if (!(COND)) { \
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std::cerr << "[Evoformer Attention]" << "'" #COND "' failed: " << ERR << "\n"; \
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return false; \
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}
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#endif
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namespace gemm_kernel_utils {
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template <typename integer>
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constexpr CUTLASS_HOST_DEVICE integer ceil_div(integer n, integer m)
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{
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return (n + m - 1) / m;
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}
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template <typename integer>
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constexpr CUTLASS_HOST_DEVICE integer align_up(integer n, integer m)
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{
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return ((n + m - 1) / m) * m;
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}
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////////////////////////////////////////////////////////////////////////////////
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// Determine the type of GEMM we do (TensorCores or not, Shapes ...)
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// TODO: Maybe we could rely on Cutlass's DefaultGemm templates
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////////////////////////////////////////////////////////////////////////////////
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// Fallback to Simt (FMA on cuda cores) if not in a special case below
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template <typename ArchTag, typename scalar_t_, typename Enable = void>
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struct DefaultGemmType {
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static constexpr int ThreadK = 8;
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static constexpr int WarpK = 8;
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static constexpr int kMinimumAlignment = 1;
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using InstructionShape = cutlass::gemm::GemmShape<1, 1, 1>;
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using OpClass = cutlass::arch::OpClassSimt;
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using Operator = cutlass::arch::OpMultiplyAdd;
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};
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// Specialization for tensorcores with f32
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template <typename ArchTag>
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struct DefaultGemmType<
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ArchTag,
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float,
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typename cutlass::platform::enable_if<ArchTag::kMinComputeCapability >= 80>::type> {
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static constexpr int ThreadK = 32;
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static constexpr int WarpK = 32;
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static constexpr int kMinimumAlignment = 4;
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using OpClass = cutlass::arch::OpClassTensorOp;
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using InstructionShape = cutlass::gemm::GemmShape<16, 8, 8>;
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using Operator = cutlass::arch::OpMultiplyAddFastF32;
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};
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// Specialization for tensorcores with f16/bf16 - Sm75+
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template <typename ArchTag, typename scalar_t>
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struct DefaultGemmType<
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ArchTag,
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scalar_t,
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typename cutlass::platform::enable_if<ArchTag::kMinComputeCapability >= 75 &&
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cutlass::sizeof_bits<scalar_t>::value == 16>::type> {
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static constexpr int ThreadK = 32;
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static constexpr int WarpK = 32;
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static constexpr int kMinimumAlignment = 4;
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using OpClass = cutlass::arch::OpClassTensorOp;
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using InstructionShape = cutlass::gemm::GemmShape<16, 8, 8>;
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using Operator = cutlass::arch::OpMultiplyAdd;
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};
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// Specialization for tensorcores with f16 - Volta
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template <>
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struct DefaultGemmType<cutlass::arch::Sm70, cutlass::half_t, void> {
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static constexpr int ThreadK = 32;
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static constexpr int WarpK = 32;
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static constexpr int kMinimumAlignment = 2;
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using OpClass = cutlass::arch::OpClassTensorOp;
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using InstructionShape = cutlass::gemm::GemmShape<8, 8, 4>;
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using Operator = cutlass::arch::OpMultiplyAdd;
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};
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// Enables to do
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// `auto x = kCondition ? fa(arg) : fb(arg)`
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// when `fa` and `fb` have different types
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template <bool kVal, typename TA, typename TB>
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struct call_conditional;
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template <typename TA, typename TB>
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struct call_conditional<true, TA, TB> {
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template <typename Arg>
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static CUTLASS_HOST_DEVICE auto apply(TA ta, TB tb, Arg arg) -> decltype(ta(arg))
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{
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return ta(arg);
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}
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};
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template <typename TA, typename TB>
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struct call_conditional<false, TA, TB> {
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template <typename Arg>
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static CUTLASS_HOST_DEVICE auto apply(TA ta, TB tb, Arg arg) -> decltype(tb(arg))
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{
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return tb(arg);
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}
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};
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////////////////////////////////////////////////////////////////////////////////
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// Mark a variable as warp-uniform - enables some compiler optimizations
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// The cheapest way to do it is just to broadcast it from lane 0
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////////////////////////////////////////////////////////////////////////////////
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CUTLASS_DEVICE int32_t warp_uniform(int32_t value)
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{
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return (int32_t)__shfl_sync(0xffffffff, (unsigned)value, 0);
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}
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template <typename T>
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CUTLASS_DEVICE T* warp_uniform(T* ptr)
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{
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struct {
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union {
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T* ptr;
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uint32_t asInt[2];
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};
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} p;
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p.ptr = ptr;
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p.asInt[0] = warp_uniform(p.asInt[0]);
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p.asInt[1] = warp_uniform(p.asInt[1]);
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return p.ptr;
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}
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} // namespace gemm_kernel_utils
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