wehub-resource-sync
63 lines
2.9 KiB
Python
63 lines
2.9 KiB
Python
# Licensed to the Apache Software Foundation (ASF) under one
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# or more contributor license agreements. See the NOTICE file
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# distributed with this work for additional information
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# regarding copyright ownership. The ASF licenses this file
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# to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance
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# with the License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing,
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# software distributed under the License is distributed on an
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# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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# KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations
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# under the License.
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"""Shared enum / value tables for PTX intrinsic schemas and user wrappers.
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Single source of truth. Both ``tvm.tirx.op`` (user wrappers that validate
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arguments via ``_choice``) and ``tvm.tirx.cuda.operator.intrinsics.*``
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(schema declarations using ``Choice(choices=...)`` / ``IntAttr(choices=...)``)
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import from here.
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Adding a new modifier value requires changing exactly one place.
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"""
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# Memory ordering / scope -----------------------------------------------------
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FENCE_SEM = ("sc", "acq_rel")
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FENCE_SCOPE = ("cta", "cluster", "gpu", "sys")
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FENCE_PROXY_ASYNC_SPACE = ("", "global", "shared::cta", "shared::cluster")
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CLUSTER_BARRIER_SEM = ("", "release", "relaxed")
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# CTA group (used by tcgen05 and TMA) -----------------------------------------
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TCGEN05_CTA_GROUP = (1, 2)
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# NVSHMEM ---------------------------------------------------------------------
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NVSHMEM_CMP = ("eq", "ne", "gt", "ge", "lt", "le")
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NVSHMEM_SIG_OP = ("set", "add")
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# Floating-point rounding -----------------------------------------------------
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F32X2_ROUND = ("rz", "rn", "rm", "rp")
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# cp.async (non-bulk) ---------------------------------------------------------
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CP_ASYNC_CACHE_HINT = ("", "evict_last", "evict_first", "evict_normal")
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CP_ASYNC_PREFETCH_SIZE = (-1, 64, 128, 256)
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CP_ASYNC_FILL_MODE = ("", "zero")
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# cp.async.bulk (TMA) ---------------------------------------------------------
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CP_ASYNC_BULK_CACHE_HINT = ("", "evict_last", "evict_first", "evict_normal", "evict_last_use")
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CP_ASYNC_BULK_RED_OP = ("add", "min", "max", "inc", "dec", "and", "or", "xor")
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# ldmatrix / stmatrix ---------------------------------------------------------
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LDMATRIX_DTYPE = (".b16", ".b8")
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LDMATRIX_NUM = (1, 2, 4)
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# tcgen05.cp ------------------------------------------------------------------
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TCGEN05_CP_SHAPES = ("32x128b", "4x256b", "128x128b", "128x256b", "64x128b")
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TCGEN05_CP_MULTICAST = ("", "warpx4", "warpx2::02_13", "warpx2::01_23")
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TCGEN05_CP_DECOMPRESS = ("", "b8x16.b4x16_p64", "b8x16.b6x16_p32")
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# tcgen05.ld / tcgen05.st -----------------------------------------------------
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TCGEN05_LDST_SHAPES = ("16x32bx2", "16x64b", "16x128b", "16x256b", "32x32b")
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