wehub-resource-sync
200 lines
7.0 KiB
Python
200 lines
7.0 KiB
Python
# Licensed to the Apache Software Foundation (ASF) under one
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# or more contributor license agreements. See the NOTICE file
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# distributed with this work for additional information
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# regarding copyright ownership. The ASF licenses this file
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# to you under the Apache License, Version 2.0 (the
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# "License"); you may not use this file except in compliance
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# with the License. You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing,
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# software distributed under the License is distributed on an
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# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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# KIND, either express or implied. See the License for the
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# specific language governing permissions and limitations
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# under the License.
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# ruff: noqa: E501, F841
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import re
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import pytest
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import tvm
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import tvm.testing
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from tvm.script import tirx as T
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from tvm.target.codegen import target_has_features
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from tvm.testing import env
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@pytest.mark.skipif(not env.has_llvm_min_version(14), reason="need llvm >= 14")
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@pytest.mark.parametrize(
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"target",
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[
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{
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"kind": "llvm",
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"device": "riscv_cpu",
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"mtriple": "riscv32-linux-gnu",
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"mcpu": "generic-rv32",
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"mattr": ["+i", "+m"],
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},
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{
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"kind": "llvm",
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"device": "riscv_cpu",
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"mtriple": "riscv32-linux-gnu",
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"mcpu": "generic-rv32",
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"mattr": ["+i", "+m", "+v"],
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},
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{
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"kind": "llvm",
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"device": "riscv_cpu",
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"mtriple": "riscv64-linux-gnu",
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"mcpu": "generic-rv64",
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"mattr": ["+64bit", "+a", "+c", "+d", "+f", "+m"],
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},
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{
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"kind": "llvm",
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"device": "riscv_cpu",
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"mtriple": "riscv64-linux-gnu",
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"mcpu": "generic-rv64",
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"mattr": ["+64bit", "+a", "+c", "+d", "+f", "+m", "+v"],
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},
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],
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)
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def test_rvv(target):
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if not tvm.testing.device_enabled(target):
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pytest.skip(f"{target} not enabled")
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def check_rvv_presence(N, extent):
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@T.prim_func(s_tir=True)
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def load_vec(A: T.Buffer((N,), "int8")):
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for j in T.vectorized(0, extent):
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A[j] = 1
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f = tvm.tirx.build(load_vec, target)
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# Check RVV `vsetvli` prensence
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assembly = f.inspect_source("asm")
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if target_has_features("v"):
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assert "vsetvli" in assembly
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else:
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assert "vsetvli" not in assembly
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with tvm.target.Target(target):
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check_rvv_presence(16, 32)
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@pytest.mark.skipif(not env.has_llvm_min_version(14), reason="need llvm >= 14")
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@pytest.mark.parametrize(
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"target",
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[
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{
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"kind": "llvm",
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"device": "riscv_cpu",
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"mtriple": "riscv32-linux-gnu",
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"mcpu": "generic-rv32",
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"mattr": ["+i", "+m", "+v"],
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},
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{
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"kind": "llvm",
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"device": "riscv_cpu",
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"mtriple": "riscv64-linux-gnu",
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"mcpu": "generic-rv64",
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"mattr": ["+64bit", "+a", "+c", "+d", "+f", "+m", "+v"],
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},
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],
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)
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def test_rvv_vscale_llvm_dbginfo(target):
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if not tvm.testing.device_enabled(target):
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pytest.skip(f"{target} not enabled")
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# fmt: off
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@T.prim_func(s_tir=True)
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def rvv_with_vscale(A_handle: T.handle, B_handle: T.handle, C_handle: T.handle):
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A = T.match_buffer(A_handle, (8,), dtype="float32", align=4, offset_factor=1)
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B = T.match_buffer(B_handle, (4, 8), dtype="float32", align=4, offset_factor=1, strides=[8, 1])
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C = T.match_buffer(C_handle, (4,), dtype="float32", align=4, offset_factor=1)
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with T.sblock("root"):
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T.reads(A[0:8], B[0:4, 0:8])
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zero = T.call_llvm_intrin("float32xvscalex2", "llvm.riscv.vfmv.v.f", T.Broadcast(T.float32(0.0), T.vscale() * 2), C[0], T.uint64(1))
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vec_A = T.call_llvm_intrin("float32xvscalex4", "llvm.riscv.vle", T.Broadcast(T.float32(0.0), T.vscale() * 4), T.tvm_access_ptr(T.type_annotation("float32"), A.data, 0, 8, 1), T.int64(8))
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vec_B = T.call_llvm_intrin("float32xvscalex4", "llvm.riscv.vle", T.Broadcast(T.float32(0.0), T.vscale() * 4), T.tvm_access_ptr(T.type_annotation("float32"), B.data, 0 * 8, 8, 1), T.int64(8))
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prod = T.call_llvm_intrin("float32xvscalex4", "llvm.riscv.vfmul", T.Broadcast(T.float32(0.0), T.vscale() * 4), vec_A, vec_B, T.uint64(7), T.uint64(8))
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redsum = T.call_llvm_intrin("float32xvscalex2", "llvm.riscv.vfredusum", T.Broadcast(T.float32(0.0), T.vscale() * 2), prod, zero, T.uint64(7), T.uint64(8))
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# fmt: on
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# tvm.error.InternalError: Can't fetch the lanes of a scalable vector at a compile time.
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with tvm.target.Target(target):
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f = tvm.tirx.build(rvv_with_vscale, target)
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@pytest.mark.skipif(not env.has_llvm_min_version(14), reason="need llvm >= 14")
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def test_rvv_fixed_width_vectorized_loop_uses_scalable_chunks():
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@T.prim_func(s_tir=True)
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def fixed16_negative(
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A: T.Buffer((14, 23, 67, 99), "float32"),
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B: T.Buffer((14, 23, 67, 99), "float32"),
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):
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for n, c, h, wo in T.grid(14, 23, 67, 7):
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for wi in T.vectorized(0, 16):
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if wo * 16 + wi < 99:
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B[n, c, h, wo * 16 + wi] = T.float32(0) - A[n, c, h, wo * 16 + wi]
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@T.prim_func(s_tir=True)
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def fixed16_negative_int64(A: T.Buffer((16,), "float32"), B: T.Buffer((16,), "float32")):
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for wi in T.vectorized(T.int64(0), T.int64(16)):
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B[wi] = T.float32(0) - A[wi]
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target = tvm.target.Target(
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{
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"kind": "llvm",
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"device": "riscv_cpu",
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"mtriple": "riscv64-linux-gnu",
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"mcpu": "generic-rv64",
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"mattr": ["+64bit", "+a", "+c", "+d", "+f", "+m", "+v"],
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}
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)
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def check_codegen(func):
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with target:
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f = tvm.tirx.build(func, target)
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assembly = f.inspect_source("asm")
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assert "vle32.v" in assembly
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assert "vse32.v" in assembly
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assert not re.search(r"\bflw\b", assembly)
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assert not re.search(r"\bfsub\.s\b", assembly)
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assert not re.search(r"\bfsw\b", assembly)
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check_codegen(fixed16_negative)
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check_codegen(fixed16_negative_int64)
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@pytest.mark.skipif(not env.has_llvm_min_version(14), reason="need llvm >= 14")
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def test_rvv_scalable_ramp_expression():
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@T.prim_func(s_tir=True)
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def ramp_compare(B: T.Buffer((16,), "int32")):
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for i in T.vectorized(16):
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B[i] = T.Select(i * 3 + 5 < 29, i * 3 + 5, -1)
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target = tvm.target.Target(
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{
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"kind": "llvm",
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"device": "riscv_cpu",
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"mtriple": "riscv64-linux-gnu",
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"mcpu": "generic-rv64",
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"mattr": ["+64bit", "+a", "+c", "+d", "+f", "+m", "+v"],
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}
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)
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with target:
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f = tvm.tirx.build(ramp_compare, target)
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assembly = f.inspect_source("asm")
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assert "vid.v" in assembly
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assert re.search(r"\bvmul\.v", assembly)
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assert re.search(r"\bvadd\.v", assembly)
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if __name__ == "__main__":
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tvm.testing.main()
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