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# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
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#
#   http://www.apache.org/licenses/LICENSE-2.0
#
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# ruff: noqa: F401, F821
import tvm
from tvm import s_tir
from tvm.script import tirx as T

# pylint: disable=no-self-argument


@tvm.script.ir_module
class WithInit:
    @T.prim_func(s_tir=True)
    def main(a: T.handle, b: T.handle) -> None:
        A = T.match_buffer(a, [64, 64, 64])
        B = T.match_buffer(b, [64])

        for i0, j0 in T.grid(64, 64):
            for k0 in T.serial(32, 64):
                with T.sblock():
                    i, j, k = T.axis.remap("SRR", [i0, j0, k0])
                    with T.init():
                        B[i] = T.float32(0)
                    B[i] += A[i, j, k]


@tvm.script.ir_module
class WithBranch:
    @T.prim_func(s_tir=True)
    def main(a: T.handle, b: T.handle) -> None:
        A = T.match_buffer(a, [64, 64, 64])
        B = T.match_buffer(b, [64])

        for i0, j0 in T.grid(64, 64):
            for k0 in T.serial(32, 64):
                with T.sblock():
                    i, j, k = T.axis.remap("SRR", [i0, j0, k0])
                    T.reads(A[i, j, k])
                    T.writes(B[i])
                    if (j == 0) and (k == 32):
                        B[i] = T.float32(0)
                    B[i] += A[i, j, k]


@tvm.script.ir_module
class InitWithMatchBuffer:
    @T.prim_func(s_tir=True)
    def main(a: T.handle, b: T.handle) -> None:
        A = T.match_buffer(a, [64, 64, 64])
        B = T.match_buffer(b, [64])

        for i0, j0 in T.grid(64, 64):
            for k0 in T.serial(32, 64):
                with T.sblock():
                    i, j, k = T.axis.remap("SRR", [i0, j0, k0])
                    BB = T.match_buffer(B[i], ())
                    AA = T.match_buffer(A[i, 0:64, 0:64], (64, 64))
                    with T.init():
                        BB[()] = T.float32(0)
                    BB[()] += AA[j, k]


@tvm.script.ir_module
class BranchWithMatchBuffer:
    @T.prim_func(s_tir=True)
    def main(a: T.handle, b: T.handle) -> None:
        A = T.match_buffer(a, [64, 64, 64])
        B = T.match_buffer(b, [64])

        for i0, j0 in T.grid(64, 64):
            for k0 in T.serial(32, 64):
                with T.sblock():
                    i, j, k = T.axis.remap("SRR", [i0, j0, k0])
                    T.reads(A[i, j, k])
                    T.writes(B[i])
                    BB = T.match_buffer(B[i], ())
                    AA = T.match_buffer(A[i, 0:64, 0:64], (64, 64))
                    if (j == 0) and (k == 32):
                        BB[()] = T.float32(0)
                    BB[()] += AA[j, k]


def test_lower_reduction():
    origin_mod = WithInit
    mod = tvm.s_tir.transform.LowerInitBlock()(origin_mod)
    tvm.ir.assert_structural_equal(mod, WithBranch, True)


def test_lower_match_buffer():
    origin_mod = InitWithMatchBuffer
    mod = tvm.s_tir.transform.LowerInitBlock()(origin_mod)
    tvm.ir.assert_structural_equal(mod, BranchWithMatchBuffer, True)


if __name__ == "__main__":
    test_lower_reduction()
    test_lower_match_buffer()
    test_lower_te()
