wehub-resource-sync
331 lines
13 KiB
Python
331 lines
13 KiB
Python
import sys
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import re
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class Assembly():
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def __init__(self, src_path, dst_path):
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self.src_path = src_path
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self.dst_path = dst_path
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# instructions
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self.ops = ['sdot', 'udot', 'smmla', 'bfmmla', 'mov', 'smopa', 'fmopa', 'luti4', 'ldr']
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def assembly(self):
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self.dst_content = []
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src = open(self.src_path, 'rt')
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for line in src.readlines():
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code = line
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cmd = code.strip().split(' ')
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for op in self.ops:
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if cmd[0] == op:
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if op == 'mov':
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code = getattr(self, op)(code, cmd[1], cmd[2])
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elif op == 'smopa' or op == 'fmopa' or op == 'luti4':
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inst = getattr(self, op)(code)
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code = code[:code.find(op)] + inst + ' // ' + code.strip(' ')
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elif op == 'ldr':
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if cmd[1] != 'zt0,':
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continue
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inst = getattr(self, op)(code)
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code = code[:code.find(op)] + inst + ' // ' + code.strip(' ')
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else:
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inst = getattr(self, op)(cmd[1], cmd[2], cmd[3])
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code = code[:code.find(op)] + inst + ' // ' + code.strip(' ')
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self.dst_content.append(code)
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src.close()
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self.write()
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def write(self):
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dst = open(self.dst_path, 'wt')
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dst.writelines(self.dst_content)
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dst.close()
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# asm parse helper function
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def gen_inst(self, opcode, flag, r1, r2, r3):
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cmd = opcode + r1 + flag + r2 + r3
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inst = '.inst ' + str(hex(int(cmd, 2)))
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return inst
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def register_to_bin(self, register):
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assert(register[0] == 'v')
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id = str(bin(int(register[1:])))[2:]
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id = '0' * (5 - len(id)) + id
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return id
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def operand_spilt(self, operand):
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v, t = operand.split('.')
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return self.register_to_bin(v), t
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def operand_to_bin(self, operand):
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r, _ = self.operand_spilt(operand)
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return r
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def t_split(self, t):
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idx = None
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if t[-1] == ']':
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t, offset = t[:-1].split('[')
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return t, int(offset)
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# instruction code gen function
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def sdot(self, operand1, operand2, operand3):
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# SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tc>[offset]
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Vd, Ta = self.operand_spilt(operand1)
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Vn, Tb = self.operand_spilt(operand2)
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Vm, Tc = self.operand_spilt(operand3)
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if "[" in Tc:
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# other flag:
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# offset = flag[4] * 2 + opcode[-1]
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# dst == '4s' ? opcode[1] = 1 : opcode[1] = 0
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Tc, offset = self.t_split(Tc)
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opcode = list('01001111100')
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flag = list('111000')
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# set Q
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if Ta == '2s' and Tb == '8b':
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opcode[1] = '0'
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# set offset
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if offset == 1 or offset == 3:
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opcode[-1] = '1'
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if offset == 2 or offset == 3:
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flag[4] = '1'
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opcode = ''.join(opcode)
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flag = ''.join(flag)
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return self.gen_inst(opcode, flag, Vm, Vn, Vd)
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else:
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opcode = list('01001110100') # different from the case with offset.
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flag = list('100101')
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# set Q
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if "2s" in Ta and "8b" in Tb:
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opcode[1] = '0'
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opcode = ''.join(opcode)
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flag = ''.join(flag)
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return self.gen_inst(opcode, flag, Vm, Vn, Vd)
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def udot(self, operand1, operand2, operand3):
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# UDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tc>[offset]
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Vd, Ta = self.operand_spilt(operand1)
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Vn, Tb = self.operand_spilt(operand2)
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Vm, Tc = self.operand_spilt(operand3)
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if "[" in Tc:
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# other flag:
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# offset = flag[4] * 2 + opcode[-1]
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# dst == '4s' ? opcode[1] = 1 : opcode[1] = 0
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Tc, offset = self.t_split(Tc)
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opcode = list('01101111100')
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flag = list('111000')
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# set Q
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if Ta == '2s' and Tb == '8b':
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opcode[1] = '0'
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# set offset
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if offset == 1 or offset == 3:
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opcode[-1] = '1'
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if offset == 2 or offset == 3:
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flag[4] = '1'
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opcode = ''.join(opcode)
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flag = ''.join(flag)
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return self.gen_inst(opcode, flag, Vm, Vn, Vd)
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else:
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opcode = list('01101110100') # different from the case with offset.
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flag = list('100101')
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# set Q
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if "2s" in Ta and "8b" in Tb:
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opcode[1] = '0'
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opcode = ''.join(opcode)
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flag = ''.join(flag)
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return self.gen_inst(opcode, flag, Vm, Vn, Vd)
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def smmla(self, operand1, operand2, operand3):
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# SMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B
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opcode = '01001110100'
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flag = '101001'
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Vd = self.operand_to_bin(operand1)
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Vn = self.operand_to_bin(operand2)
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Vm = self.operand_to_bin(operand3)
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return self.gen_inst(opcode, flag, Vm, Vn, Vd)
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def bfmmla(self, operand1, operand2, operand3):
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# BFMMLA <Vd>.4S, <Vn>.8H, <Vm>.8H
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opcode = '01101110010'
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flag = '111011'
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Vd = self.operand_to_bin(operand1)
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Vn = self.operand_to_bin(operand2)
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Vm = self.operand_to_bin(operand3)
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return self.gen_inst(opcode, flag, Vm, Vn, Vd)
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def mov(self, code, operand1, operand2):
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# compile failed using `mov v1.8h, v2.8h`
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# change to `mov v1.16b, v2.16b`
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if '.8h' not in operand1 or '.8h' not in operand2:
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return code
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operand1 = operand1.replace('8h', '16b')
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operand2 = operand2.replace('8h', '16b')
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new_mov = f'mov {operand1} {operand2}'
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new_code = code[:code.find('mov')] + new_mov + ' // ' + code.strip(' ')
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return new_code
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def smopa(self, instruction):
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"""
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SMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.B, <Zm>.B 32bit 4-way
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SMOPA <ZAda>.D, <Pn>/M, <Pm>/M, <Zn>.H, <Zm>.H 64bit 4-way
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"""
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try:
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parts = instruction.replace(' ', '').split(',')
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if len(parts) != 5:
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raise ValueError("smopa 指令格式错误")
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zda = int(parts[0].split('za')[1].split('.')[0])
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pn = int(parts[1].split('p')[1].split('/')[0])
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pm = int(parts[2].split('p')[1].split('/')[0])
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zn = int(parts[3].split('z')[1].split('.')[0])
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zm = int(parts[4].split('z')[1].split('.')[0])
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zmDataType = parts[4].split('z')[1].split('.')[1][0]
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if not (0 <= zda <= 15):
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raise ValueError("zda必须在0-15范围内")
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if not (0 <= pn <= 7):
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raise ValueError("pg必须在0-7范围内")
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if not (0 <= pn <= 7):
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raise ValueError("pn必须在0-7范围内")
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if not (0 <= zm <= 31):
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raise ValueError("zm必须在0-31范围内")
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if not (0 <= zn <= 31):
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raise ValueError("zn必须在0-31范围内")
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# smopa za0.s, p3/m, p4/m, z0.b, z1.b
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is32Bit4way = (parts[0].split('za')[1].split('.')[1] == "s") and (parts[3].split('z')[1].split('.')[1] == 'b') and (zmDataType == 'b')
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# smopa za0.d, p3/m, p4/m, z0.h, z1.h
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is64Bit4way = (parts[0].split('za')[1].split('.')[1] == "d") and (parts[3].split('z')[1].split('.')[1] == 'h') and (zmDataType == 'h')
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# smopa za0.s, p3/m, p4/m, z0.h, z1.h
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is2way = (parts[0].split('za')[1].split('.')[1] == "s") and (parts[3].split('z')[1].split('.')[1] == 'h') and (zmDataType == 'h')
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if (is32Bit4way == False) and (is64Bit4way == False) and (is2way):
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raise ValueError("smopa 指令格式错误")
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# is32Bit4way
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opcode = "10100000100" #[31, 21]
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zmCode = format(zm, '05b') # zm register has '5' bit,[20, 16]
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pmCode = format(pm, '03b') # pm register has '3' bit,[15,13]
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pnCode = format(pn, '03b') # pn register has '3' bit,[12,10]
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znCode = format(zn, '05b') # zn register has '5' bit, [9,5]
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fixCode = "000" # fixed encode
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zaCode = format(zda, '02b') # za register has '2' bit, [1,0]
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if is64Bit4way == True:
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opcode = "10100000110"
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fixCode = "00"
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zaCode = format(zda, '03b')
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elif is2way == True:
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opcode = "10100000100"
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fixCode = "010"
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# concact
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binary = opcode + zmCode + pmCode + pnCode + znCode + fixCode + zaCode
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inst = '.inst ' + str(hex(int(binary, 2)))
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return inst
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except Exception as e:
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raise ValueError(f"smopa 指令解析错误: {str(e)}")
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def fmopa(self, instruction):
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'''
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FMOPA <ZAda>.S, <Pn>/M, <Pm>/M, <Zn>.S, <Zm>.S
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'''
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try:
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parts = instruction.replace(' ', '').split(',')
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if len(parts) != 5:
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raise ValueError("fmopa 指令格式错误")
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zda = int(parts[0].split('za')[1].split('.')[0])
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pn = int(parts[1].split('p')[1].split('/')[0])
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pm = int(parts[2].split('p')[1].split('/')[0])
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zn = int(parts[3].split('z')[1].split('.')[0])
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zm = int(parts[4].split('z')[1].split('.')[0])
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zmDataType = parts[4].split('z')[1].split('.')[1][0]
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# fmopa za0.s, p3/m, p4/m, z0.s, z1.s
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singlePrecisionNotWidening = (parts[0].split('za')[1].split('.')[1] == "s") and (parts[3].split('z')[1].split('.')[1] == 's') and (zmDataType == 's')
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# fmopa za0.s, p3/m, p3/m, z0.h, z1.h
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fp16Tofp32 = (parts[0].split('za')[1].split('.')[1] == "s") and (parts[3].split('z')[1].split('.')[1] == 'h') and (zmDataType == 'h')
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if not singlePrecisionNotWidening and not fp16Tofp32:
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raise ValueError("Not implement yet\n")
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opcode = "10000000100"
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zmCode = format(zm, '05b') # zm register has '5' bit,[20, 16]
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pmCode = format(pm, '03b') # pm register has '3' bit,[15,13]
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pnCode = format(pn, '03b') # pn register has '3' bit,[12,10]
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znCode = format(zn, '05b') # zn register has '5' bit, [9,5]
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fixCode = "000" # fixed encode
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zaCode = format(zda, '02b') # za register has '2' bit, [1,0]
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if fp16Tofp32 == True:
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opcode = "10000001101"
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binary = opcode + zmCode + pmCode + pnCode + znCode + fixCode + zaCode
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inst = '.inst ' + str(hex(int(binary, 2)))
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return inst
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except Exception as e:
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raise ValueError(f"fmopa 指令解析错误: {str(e)}")
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def luti4(self, instruction):
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'''
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luti4 {z2.b-z3.b}, zt0, z1[0]
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'''
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try:
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parts = instruction.replace(' ', '').split(',')
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if len(parts) != 3:
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raise ValueError("luti4 指令格式错误")
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# 解析目标寄存器
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zd = int(parts[0].split('z')[1].split('.')[0])
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T = parts[0].split('.')[1].split('.')[0][0]
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if T != 'b':
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raise ValueError("Not implement yet\n")
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# 解析查找表寄存器
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zt = int(parts[1].split('zt')[1])
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# 解析源寄存器
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zn = int(parts[2].split('z')[1].split('[')[0])
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i2 = int(parts[2].split('z')[1].split('[')[1][0])
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opcode = "110000001000101"
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i2code = format(i2, '02b')
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constcode0 = "1"
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sizecode = "00" # b
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constcode1 = "00"
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zncode = format(zn, '05b')
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zdcode = format(zd, '05b')
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binary = opcode + i2code + constcode0 + sizecode + constcode1 + zncode + zdcode
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inst = '.inst ' + str(hex(int(binary, 2)))
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return inst
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except Exception as e:
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raise ValueError(f"luti4 指令解析错误: {str(e)}")
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def ldr(self, instruction):
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'''
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.inst 0xe11f8100 // ldr zt0, [x8]
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'''
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i0 = instruction.find('[')
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i1 = instruction.find(']')
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x = int(instruction[i0 + 2: i1])
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opcode = "1110000100011111100000"
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rn = format(x, '05b')
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fixcode = "00000"
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binary = opcode + rn + fixcode
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inst = '.inst ' + str(hex(int(binary, 2)))
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return inst
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if __name__ == '__main__':
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if len(sys.argv) < 2:
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print('Usage: python arm_asselmbly.py src.asm [dst.asm]')
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src_file = sys.argv[1]
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if len(sys.argv) > 2:
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dst_file = sys.argv[2]
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else:
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dst_file = src_file
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a = Assembly(src_file, dst_file)
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a.assembly()
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