wehub-resource-sync
132 lines
9.0 KiB
C++
132 lines
9.0 KiB
C++
//
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// CutlassGemmTuneCommonExecution.hpp
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// MNN
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//
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// Created by MNN on 2023/10/09.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef ENABLE_CUDA_TUNE_PARAM
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#ifndef CutlassGemmTuneCommonExecution_hpp
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#define CutlassGemmTuneCommonExecution_hpp
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#include "backend/cuda/core/CUDABackend.hpp"
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#include "core/Execution.hpp"
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#include "execution/cutlass_common/tune/CutlassGemmTune.hpp"
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namespace MNN {
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namespace CUDA {
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class CutlassGemmTuneCommonExecution : public Execution {
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public:
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CutlassGemmTuneCommonExecution(Backend* backend) : Execution(backend) {};
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virtual ~CutlassGemmTuneCommonExecution() = default;
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void setGemmBatchedTensorCoreFloat16Argments(const GemmParamInfo* params);
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void runGemmBatchedTensorCoreFloat16Infer(const GemmParamInfo* params);
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void setGemmTensorCoreFloat16Argments(const GemmParamInfo* params);
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void runGemmTensorCoreFloat16Infer(const GemmParamInfo* params);
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protected:
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GemmParamInfo mInfo;
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// GemmBatched
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_64x64x32 mGemmBatchedF16F16TensorAlign8RC_64x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_64x64x64 mGemmBatchedF16F16TensorAlign8RC_64x64x64;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_64x128x32 mGemmBatchedF16F16TensorAlign8RC_64x128x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_128x64x32 mGemmBatchedF16F16TensorAlign8RC_128x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_128x64x64 mGemmBatchedF16F16TensorAlign8RC_128x64x64;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_256x64x32 mGemmBatchedF16F16TensorAlign8RC_256x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_128x128x32 mGemmBatchedF16F16TensorAlign8RC_128x128x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Column_Sm80_64x64x32 mGemmBatchedF16F16TensorAlign1RC_64x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Column_Sm80_64x64x64 mGemmBatchedF16F16TensorAlign1RC_64x64x64;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Column_Sm80_64x128x32 mGemmBatchedF16F16TensorAlign1RC_64x128x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Column_Sm80_128x64x32 mGemmBatchedF16F16TensorAlign1RC_128x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Column_Sm80_128x64x64 mGemmBatchedF16F16TensorAlign1RC_128x64x64;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Column_Sm80_256x64x32 mGemmBatchedF16F16TensorAlign1RC_256x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Column_Sm80_128x128x32 mGemmBatchedF16F16TensorAlign1RC_128x128x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Row_Sm80_64x64x32 mGemmBatchedF16F16TensorAlign8RR_64x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Row_Sm80_64x64x64 mGemmBatchedF16F16TensorAlign8RR_64x64x64;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Row_Sm80_64x128x32 mGemmBatchedF16F16TensorAlign8RR_64x128x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Row_Sm80_128x64x32 mGemmBatchedF16F16TensorAlign8RR_128x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Row_Sm80_128x64x64 mGemmBatchedF16F16TensorAlign8RR_128x64x64;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Row_Sm80_256x64x32 mGemmBatchedF16F16TensorAlign8RR_256x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Row_Sm80_128x128x32 mGemmBatchedF16F16TensorAlign8RR_128x128x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Row_Sm80_64x64x32 mGemmBatchedF16F16TensorAlign1RR_64x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Row_Sm80_64x64x64 mGemmBatchedF16F16TensorAlign1RR_64x64x64;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Row_Sm80_64x128x32 mGemmBatchedF16F16TensorAlign1RR_64x128x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Row_Sm80_128x64x32 mGemmBatchedF16F16TensorAlign1RR_128x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Row_Sm80_128x64x64 mGemmBatchedF16F16TensorAlign1RR_128x64x64;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Row_Sm80_256x64x32 mGemmBatchedF16F16TensorAlign1RR_256x64x32;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Row_Sm80_128x128x32 mGemmBatchedF16F16TensorAlign1RR_128x128x32;
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// // Gemm Linear
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GemmTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_64x64x32 mGemmF16F16TensorLnAlign8RC_64x64x32;
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GemmTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_64x64x64 mGemmF16F16TensorLnAlign8RC_64x64x64;
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GemmTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_64x128x32 mGemmF16F16TensorLnAlign8RC_64x128x32;
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GemmTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_128x64x32 mGemmF16F16TensorLnAlign8RC_128x64x32;
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GemmTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_128x64x64 mGemmF16F16TensorLnAlign8RC_128x64x64;
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GemmTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_256x64x32 mGemmF16F16TensorLnAlign8RC_256x64x32;
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GemmTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm80_128x128x32 mGemmF16F16TensorLnAlign8RC_128x128x32;
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GemmTensor_F16_F32_Linear_AlignTensor_Row_Column_Sm80_64x64x32 mGemmF16F32TensorLnAlign8RC_64x64x32;
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GemmTensor_F16_F32_Linear_AlignTensor_Row_Column_Sm80_64x64x64 mGemmF16F32TensorLnAlign8RC_64x64x64;
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GemmTensor_F16_F32_Linear_AlignTensor_Row_Column_Sm80_64x128x32 mGemmF16F32TensorLnAlign8RC_64x128x32;
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GemmTensor_F16_F32_Linear_AlignTensor_Row_Column_Sm80_128x64x32 mGemmF16F32TensorLnAlign8RC_128x64x32;
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GemmTensor_F16_F32_Linear_AlignTensor_Row_Column_Sm80_128x64x64 mGemmF16F32TensorLnAlign8RC_128x64x64;
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GemmTensor_F16_F32_Linear_AlignTensor_Row_Column_Sm80_256x64x32 mGemmF16F32TensorLnAlign8RC_256x64x32;
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GemmTensor_F16_F32_Linear_AlignTensor_Row_Column_Sm80_128x128x32 mGemmF16F32TensorLnAlign8RC_128x128x32;
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// // Gemm Relu
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GemmTensor_F16_F16_Relu_AlignTensor_Row_Column_Sm80_64x64x32 mGemmF16F16TensorReluAlign8RC_64x64x32;
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GemmTensor_F16_F16_Relu_AlignTensor_Row_Column_Sm80_64x64x64 mGemmF16F16TensorReluAlign8RC_64x64x64;
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GemmTensor_F16_F16_Relu_AlignTensor_Row_Column_Sm80_64x128x32 mGemmF16F16TensorReluAlign8RC_64x128x32;
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GemmTensor_F16_F16_Relu_AlignTensor_Row_Column_Sm80_128x64x32 mGemmF16F16TensorReluAlign8RC_128x64x32;
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GemmTensor_F16_F16_Relu_AlignTensor_Row_Column_Sm80_128x64x64 mGemmF16F16TensorReluAlign8RC_128x64x64;
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GemmTensor_F16_F16_Relu_AlignTensor_Row_Column_Sm80_256x64x32 mGemmF16F16TensorReluAlign8RC_256x64x32;
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GemmTensor_F16_F16_Relu_AlignTensor_Row_Column_Sm80_128x128x32 mGemmF16F16TensorReluAlign8RC_128x128x32;
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GemmTensor_F16_F32_Relu_AlignTensor_Row_Column_Sm80_64x64x32 mGemmF16F32TensorReluAlign8RC_64x64x32;
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GemmTensor_F16_F32_Relu_AlignTensor_Row_Column_Sm80_64x64x64 mGemmF16F32TensorReluAlign8RC_64x64x64;
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GemmTensor_F16_F32_Relu_AlignTensor_Row_Column_Sm80_64x128x32 mGemmF16F32TensorReluAlign8RC_64x128x32;
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GemmTensor_F16_F32_Relu_AlignTensor_Row_Column_Sm80_128x64x32 mGemmF16F32TensorReluAlign8RC_128x64x32;
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GemmTensor_F16_F32_Relu_AlignTensor_Row_Column_Sm80_128x64x64 mGemmF16F32TensorReluAlign8RC_128x64x64;
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GemmTensor_F16_F32_Relu_AlignTensor_Row_Column_Sm80_256x64x32 mGemmF16F32TensorReluAlign8RC_256x64x32;
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GemmTensor_F16_F32_Relu_AlignTensor_Row_Column_Sm80_128x128x32 mGemmF16F32TensorReluAlign8RC_128x128x32;
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// // Gemm Relu6
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GemmTensor_F16_F16_Relu6_AlignTensor_Row_Column_Sm80_64x64x32 mGemmF16F16TensorRelu6Align8RC_64x64x32;
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GemmTensor_F16_F16_Relu6_AlignTensor_Row_Column_Sm80_64x64x64 mGemmF16F16TensorRelu6Align8RC_64x64x64;
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GemmTensor_F16_F16_Relu6_AlignTensor_Row_Column_Sm80_64x128x32 mGemmF16F16TensorRelu6Align8RC_64x128x32;
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GemmTensor_F16_F16_Relu6_AlignTensor_Row_Column_Sm80_128x64x32 mGemmF16F16TensorRelu6Align8RC_128x64x32;
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GemmTensor_F16_F16_Relu6_AlignTensor_Row_Column_Sm80_128x64x64 mGemmF16F16TensorRelu6Align8RC_128x64x64;
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GemmTensor_F16_F16_Relu6_AlignTensor_Row_Column_Sm80_256x64x32 mGemmF16F16TensorRelu6Align8RC_256x64x32;
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GemmTensor_F16_F16_Relu6_AlignTensor_Row_Column_Sm80_128x128x32 mGemmF16F16TensorRelu6Align8RC_128x128x32;
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GemmTensor_F16_F32_Relu6_AlignTensor_Row_Column_Sm80_64x64x32 mGemmF16F32TensorRelu6Align8RC_64x64x32;
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GemmTensor_F16_F32_Relu6_AlignTensor_Row_Column_Sm80_64x64x64 mGemmF16F32TensorRelu6Align8RC_64x64x64;
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GemmTensor_F16_F32_Relu6_AlignTensor_Row_Column_Sm80_64x128x32 mGemmF16F32TensorRelu6Align8RC_64x128x32;
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GemmTensor_F16_F32_Relu6_AlignTensor_Row_Column_Sm80_128x64x32 mGemmF16F32TensorRelu6Align8RC_128x64x32;
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GemmTensor_F16_F32_Relu6_AlignTensor_Row_Column_Sm80_128x64x64 mGemmF16F32TensorRelu6Align8RC_128x64x64;
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GemmTensor_F16_F32_Relu6_AlignTensor_Row_Column_Sm80_256x64x32 mGemmF16F32TensorRelu6Align8RC_256x64x32;
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GemmTensor_F16_F32_Relu6_AlignTensor_Row_Column_Sm80_128x128x32 mGemmF16F32TensorRelu6Align8RC_128x128x32;
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int mGpuComputeCap = 75;
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int mActivationType = 0;
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bool mFp16Infer = false;
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bool mFp32Infer = false;
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bool mFp16Fp32MixInfer = false;
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bool mBf16Infer = false;
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int mPrecisonLevel;
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std::shared_ptr<Tensor> workspaceTensor;
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void* mWorkspace;
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};
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} // namespace CUDA
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} // namespace MNN
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#endif /* CutlassGemmTuneCommonExecution */
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#endif |