wehub-resource-sync
114 lines
3.0 KiB
C++
114 lines
3.0 KiB
C++
//
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// CutlassDeconvCommonExecution.hpp
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// MNN
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//
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// Created by MNN on 2023/04/25.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifndef CutlassDeconvCommonExecution_hpp
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#define CutlassDeconvCommonExecution_hpp
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#include "backend/cuda/core/CUDABackend.hpp"
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#include "core/Execution.hpp"
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#include "../CutlassGemmParam.hpp"
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#include "../MNNCUDADefine.hpp"
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#include "../MNNCUDAFunction.cuh"
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namespace MNN {
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namespace CUDA {
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struct KernelInfo {
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int groups = 0;
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int kernelN = 0;
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int kernelC = 0;
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int kernelX = 0;
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int kernelY = 0;
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int strideX = 0;
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int strideY = 0;
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int dilateX = 0;
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int dilateY = 0;
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int activationType = 0;
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};//
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struct Col2ImParameter {
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int padX;
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int padY;
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int dilateX;
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int dilateY;
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int strideX;
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int strideY;
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int kernelX;
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int kernelY;
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int oc;
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int ic;
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int iw;
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int ih;
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int ow;
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int oh;
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int ob;
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int activationType;
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};
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class CutlassDeconvCommonExecution : public Execution {
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public:
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CutlassDeconvCommonExecution(Backend* backend);
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virtual ~CutlassDeconvCommonExecution() = default;
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ErrorCode callCutlassGemmCudaCoreFloat16(const std::vector<Tensor*> &inputs, const std::vector<Tensor*> &outputs);
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ErrorCode callCutlassGemmCudaCoreFloat32(const std::vector<Tensor*> &inputs, const std::vector<Tensor*> &outputs);
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ErrorCode callCutlassGemmTensorCore(const std::vector<Tensor*> &inputs, const std::vector<Tensor*> &outputs);
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ErrorCode runCutlassGemmFunc();
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protected:
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Backend* mBackendPtr;
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void* mFilterAddr;
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void* mBiasAddr = nullptr;
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CutlassGemmInfo mGemmInfo;
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const Op* mOp = nullptr;
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Col2ImParameter mCol2ImParamter;
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int mActivationType;
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int mGpuComputeCap;
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void* mIm2ColBuffer;
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void* mInputBuffer;
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std::shared_ptr<Tensor> workspaceTensor;
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void* mWorkspace;
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void* mZeroPtr;
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std::shared_ptr<Tensor> mZeroTensor;
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bool mFp16Infer = false;
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bool mFp32Infer = false;
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bool mFp16Fp32MixInfer = false;
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int mPrecisonLevel;
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GemmCuda_F16_F16_Linear_AlignCuda mGemmCudaF16F16Ln;
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GemmCuda_F16_F32_Linear_AlignCuda mGemmCudaF16F32Ln;
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GemmCuda_F32_F32_Linear_AlignCuda mGemmCudaF32F32Ln;
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GemmCuda_F16_F16_Relu_AlignCuda mGemmCudaF16F16Relu;
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GemmCuda_F16_F32_Relu_AlignCuda mGemmCudaF16F32Relu;
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GemmCuda_F32_F32_Relu_AlignCuda mGemmCudaF32F32Relu;
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GemmCuda_F16_F16_Relu6_AlignCuda mGemmCudaF16F16Relu6;
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GemmCuda_F16_F32_Relu6_AlignCuda mGemmCudaF16F32Relu6;
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GemmCuda_F32_F32_Relu6_AlignCuda mGemmCudaF32F32Relu6;
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GemmTensor_F16_F16_Linear_AlignCuda_Sm75 mGemmF16F16LnSm75;
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GemmTensor_F16_F32_Linear_AlignCuda_Sm75 mGemmF16F32LnSm75;
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GemmTensor_F16_F16_Relu_AlignCuda_Sm75 mGemmF16F16ReluSm75;
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GemmTensor_F16_F32_Relu_AlignCuda_Sm75 mGemmF16F32ReluSm75;
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GemmTensor_F16_F16_Relu6_AlignCuda_Sm75 mGemmF16F16Relu6Sm75;
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GemmTensor_F16_F32_Relu6_AlignCuda_Sm75 mGemmF16F32Relu6Sm75;
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};
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} // namespace CUDA
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} // namespace MNN
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#endif /* CutlassDeconvCommonExecution */
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