wehub-resource-sync
179 lines
3.1 KiB
ArmAsm
179 lines
3.1 KiB
ArmAsm
//
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// MNNReluWithSlopeChannel.S
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// MNN
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//
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// Created by MNN on 2023/07/06.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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/*
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struct QuanPrePostParameters{
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float* inputScale;
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float* outputScale;
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ssize_t* inputZeroPoint;
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ssize_t* outputZeroPoint;
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ssize_t minValue;
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ssize_t maxValue;
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};
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*/
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#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNReluWithSlopeChannelInt8
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// MNNReluWithSlopeChannelInt8(int8_t* dst, const int8_t* src, const float* slope, size_t planeNumber, size_t depthQuad, QuanPrePostParameters *params)
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// Auto load:
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// x0: dst, x1: src, x2: slope, x3: planeNumber, x4: depthQuad, x5: params
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// Load from x5: x9: outputZeroPoint, x10: minValue, x11: maxValue
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ldr x12, [x5, #0]
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ldr x13, [x5, #8]
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ldr x8, [x5, #16]
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ldr x9, [x5, #24]
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ldr x10, [x5, #32]
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ldr x11, [x5, #40]
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stp d14, d15, [sp, #-64]!
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stp d12, d13, [sp, #16]
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stp d10, d11, [sp, #32]
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stp d8, d9, [sp, #48]
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cmp x3, #0
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beq End
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cmp x4, #0
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beq End
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ld1r {v29.16b}, [x8] // inputZeroPoint
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ld1r {v28.16b}, [x9] // outputZeroPoint
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dup v26.16b, w10
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dup v27.16b, w11
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ld1r {v24.4s}, [x12] // inputscale
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ld1r {v25.4s}, [x13] // outputscale
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/*
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Quant parameters
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*/
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PReluZLoop:
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ld1 {v31.4s}, [x2], #16 // slope
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mov x5, x3
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cmp x5, #3
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ble PReluL1
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PReluL4Loop:
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ld1 {v0.16b}, [x1], #16
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sxtl v1.8h, v0.8b
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sxtl2 v2.8h, v0.16b
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ssubw v1.8h, v1.8h, v29.8b
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ssubw v2.8h, v2.8h, v29.8b
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sxtl v3.4s, v1.4h
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sxtl2 v4.4s, v1.8h
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sxtl v5.4s, v2.4h
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sxtl2 v6.4s, v2.8h
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scvtf v3.4s, v3.4s
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scvtf v4.4s, v4.4s
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scvtf v5.4s, v5.4s
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scvtf v6.4s, v6.4s
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// input_scale
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fmul v3.4s, v3.4s, v24.4s
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fmul v4.4s, v4.4s, v24.4s
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fmul v5.4s, v5.4s, v24.4s
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fmul v6.4s, v6.4s, v24.4s
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fcmle v7.4s, v3.4s, #0
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fcmle v8.4s, v4.4s, #0
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fcmle v9.4s, v5.4s, #0
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fcmle v10.4s, v6.4s, #0
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// *slope
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fmul v11.4s, v3.4s, v31.4s
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fmul v12.4s, v4.4s, v31.4s
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fmul v13.4s, v5.4s, v31.4s
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fmul v14.4s, v6.4s, v31.4s
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bit v3.16b, v11.16b, v7.16b
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bit v4.16b, v12.16b, v8.16b
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bit v5.16b, v13.16b, v9.16b
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bit v6.16b, v14.16b, v10.16b
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// *output_scale
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fmul v3.4s, v3.4s, v25.4s
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fmul v4.4s, v4.4s, v25.4s
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fmul v5.4s, v5.4s, v25.4s
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fmul v6.4s, v6.4s, v25.4s
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fcvtas v3.4s, v3.4s
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fcvtas v4.4s, v4.4s
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fcvtas v5.4s, v5.4s
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fcvtas v6.4s, v6.4s
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sqxtn v7.4h, v3.4s
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sqxtn2 v7.8h, v4.4s
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sqxtn v8.4h, v5.4s
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sqxtn2 v8.8h, v6.4s
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saddw v7.8h, v7.8h, v28.8b
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saddw v8.8h, v8.8h, v28.8b
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sqxtn v9.8b, v7.8h
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sqxtn2 v9.16b, v8.8h
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smax v9.16b, v9.16b, v26.16b
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smin v9.16b, v9.16b, v27.16b
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st1 {v9.16b}, [x0], #16
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sub x5, x5, #4
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cmp x5, #4
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bge PReluL4Loop
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PReluL1:
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cmp x5, #0
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beq PReluL1End
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PReluL1Loop:
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ld1 {v0.s}[0], [x1], #4
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sxtl v1.8h, v0.8b
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ssubw v1.8h, v1.8h, v29.8b
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sxtl v1.4s, v1.4h
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scvtf v1.4s, v1.4s
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// *input_scale
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fmul v1.4s, v1.4s, v24.4s
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fcmle v7.4s, v1.4s, #0
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// *slope
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fmul v11.4s, v1.4s, v31.4s
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bit v1.16b, v11.16b, v7.16b
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// *output_scale
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fmul v1.4s, v1.4s, v25.4s
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fcvtas v1.4s, v1.4s
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sqxtn v1.4h, v1.4s
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saddw v1.8h, v1.8h, v28.8b
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sqxtn v1.8b, v1.8h
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smax v1.8b, v1.8b, v26.8b
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smin v1.8b, v1.8b, v27.8b
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st1 {v1.s}[0], [x0], #4
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subs x5, x5, #1
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bne PReluL1Loop
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PReluL1End:
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subs x4, x4, #1
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bne PReluZLoop
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End:
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ldp d8, d9, [sp, #48]
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ldp d10, d11, [sp, #32]
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ldp d12, d13, [sp, #16]
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ldp d14, d15, [sp], #64
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ret
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#endif
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