wehub-resource-sync
214 lines
3.5 KiB
ArmAsm
214 lines
3.5 KiB
ArmAsm
//
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// MNNMaxPoolInt8.s
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// ALL_BUILD
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//
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// Created by MNN on 2023/1/9.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNMaxPoolInt8
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// void MNNMaxPoolInt8(int8_t* dst, int8_t* src, size_t outputWidth, size_t inputWidth, size_t kernelx, size_t kernely,
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// size_t stridesx);
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// Auto load: x0: dst, x1: src, x2: outputWidth, x3: inputWidth, x4: kernelx, x5: kernely, x6: stridesx
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sub sp, sp, #32
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str x19, [sp, #0]
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str x20, [sp, #8]
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str x21, [sp, #16]
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cmp x4, #0
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ble END
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cmp x5, #0
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ble END
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mov x9, #16
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mul x9, x9, x3 // x9: 16*inputWidth
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mov x8, #16
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mul x8, x8, x6 // x8: 16*stridesx
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cmp x2, #4
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blt L1Loop
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cmp x2, #8
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blt L4Loop
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/*L8Loop */
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L8Loop:
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mov x14, #4
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mul x14, x14, x8 // x14: 64*stridesx
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mov w7, #-0x80
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dup v0.16b, w7
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dup v1.16b, w7
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dup v2.16b, w7
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dup v3.16b, w7
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dup v16.16b, w7
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dup v17.16b, w7
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dup v18.16b, w7
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dup v19.16b, w7
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mov x10, x5 // x5: kernely
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mov x13, x1
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Loop8Y:
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mov x7, x4 // x4: kernelx
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mov x3, x13
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add x15, x13, x14
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add x11, x3, x8
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add x19, x15, x8
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add x6, x11, x8
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add x20, x19, x8
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add x12, x6, x8
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add x21, x20, x8
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Loop8X:
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ld1 {v4.16b}, [x3], #16
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ld1 {v5.16b}, [x11], #16
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ld1 {v6.16b}, [x6], #16
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ld1 {v7.16b}, [x12], #16
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ld1 {v20.16b}, [x15], #16
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ld1 {v21.16b}, [x19], #16
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ld1 {v22.16b}, [x20], #16
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ld1 {v23.16b}, [x21], #16
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smax v0.16b, v0.16b, v4.16b
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smax v1.16b, v1.16b, v5.16b
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smax v2.16b, v2.16b, v6.16b
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smax v3.16b, v3.16b, v7.16b
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smax v16.16b, v16.16b, v20.16b
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smax v17.16b, v17.16b, v21.16b
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smax v18.16b, v18.16b, v22.16b
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smax v19.16b, v19.16b, v23.16b
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sub x7, x7, #1 // x7: kernelx
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cmp x7, #0
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bne Loop8X
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EndLoop8X:
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add x13, x13, x9
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sub x10, x10, #1 // x10: kernely
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cmp x10, #0
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bne Loop8Y
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EndLoop8Y:
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st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #64
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st1 {v16.16b, v17.16b, v18.16b, v19.16b}, [x0], #64
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mov x3, #8
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mul x3, x3, x8 // x3: 128* strides
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add x1, x1, x3
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sub x2, x2, #8 // x2: OutputWidth
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cmp x2, #8
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bge L8Loop
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cmp x2, #4
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bge L4Loop
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cmp x2, #1
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bge L1Loop
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cmp x2, #0
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beq END
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/*L4Loop */
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L4Loop:
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mov w7, #-0x80
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dup v0.16b, w7
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dup v1.16b, w7
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dup v2.16b, w7
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dup v3.16b, w7
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mov x10, x5 // x5: kernely
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mov x13, x1
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Loop4Y:
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mov x7, x4 // x4: kernelx
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mov x3, x13
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add x11, x3, x8
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add x6, x11, x8
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add x12, x6, x8
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Loop4X:
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ld1 {v4.16b}, [x3], #16
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ld1 {v5.16b}, [x11], #16
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ld1 {v6.16b}, [x6], #16
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ld1 {v7.16b}, [x12], #16
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smax v0.16b, v0.16b, v4.16b
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smax v1.16b, v1.16b, v5.16b
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smax v2.16b, v2.16b, v6.16b
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smax v3.16b, v3.16b, v7.16b
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sub x7, x7, #1 // x7: kernelx
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cmp x7, #0
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bne Loop4X
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EndLoop4X:
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add x13, x13, x9
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sub x10, x10, #1 // x10: kernely
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cmp x10, #0
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bne Loop4Y
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EndLoop4Y:
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st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #64
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mov x3, #4
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mul x3, x3, x8 // x3: 64* strides
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add x1, x1, x3
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sub x2, x2, #4 // x2: OutputWidth
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cmp x2, #4
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bge L4Loop
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cmp x2, #0
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beq END
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/* L1Loop */
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L1Loop:
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mov w7, #-0x80
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dup v0.16b, w7
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mov x10, x5 // x10: kernely
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mov x12, x1 // x1: src
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L1LoopY:
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mov x7, x4 // x7: kernelx
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mov x3, x12 // x12: src
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L1LoopX:
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ld1 {v1.16b}, [x3], #16
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smax v0.16b, v0.16b, v1.16b
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sub x7, x7, #1
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cmp x7, #0
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bne L1LoopX
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add x12, x12, x9
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sub x10, x10, #1
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cmp x10, #0
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bne L1LoopY
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st1 {v0.16b}, [x0], #16
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add x1, x1, x8
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sub x2, x2, #1 // x2: OutputWidth
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cmp x2, #0
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bgt L1Loop
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beq END
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END:
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ldr x19, [sp, #0]
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ldr x20, [sp, #8]
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ldr x21, [sp, #16]
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add sp, sp, #32
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ret
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#endif |