wehub-resource-sync
187 lines
3.6 KiB
ArmAsm
187 lines
3.6 KiB
ArmAsm
// MNNCubicSampleC16.S
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// MNN
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//
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// Created by MNN on 2019/01/18.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNCubicSampleC16
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// void MNNCubicSampleC16(const int8_t* src, float* dst, int32_t* position, const float* factor, int8_t* zeroPoint, size_t number)
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// Auto load:
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// x0: src, x1: dst, x2: position, x3: factor, x4: zeroPoint, x5: number
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stp d14, d15, [sp, #-64]!
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stp d12, d13, [sp, #16]
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stp d10, d11, [sp, #32]
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stp d8, d9, [sp, #48]
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cmp x5, #0
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beq END
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mov w15, #16
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uxtw x15, w15
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L1Loop:
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ld1 {v31.s}[0], [x3], #4
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fmov s1, #1.0
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dup v31.4s, v31.s[0] // v31: t
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fmov s30, #1.0
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fsub s30, s30, s31 // 1-t
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fmul s29, s31, s31 // t^2
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fmul s28, s30, s30 // (1-t)^2
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fmul s27, s31, s29 // t^3
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fmul s26, s28, s30 // (1-t)^3
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fmov s25, #-2.25
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fmov s24, #1.25
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fmul s27, s27, s24
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fmul s26, s26, s24
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fmla s27, s25, v29.s[0]
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fmla s26, s25, v28.s[0]
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fadd s27, s27, s1 // bo
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fadd s26, s26, s1 // c0
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dup v3.4s, v27.s[0] // b0
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dup v29.4s, v26.s[0] // c0
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fadd s23, s31, s1 // t_a
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fmul s22, s23, s23 // t_a^2
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fmul s21, s22, s23 // t_a^3
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fadd s20, s30, s1 // t_b
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fmul s19, s20, s20 // t_b^2
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fmul s18, s19, s20 // t_b^3
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fmov s31, #-0.75
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fmov s30, #3.75
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fmov s24, #-6.0
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fmov s25, #3.0
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fmul s21, s21, s31
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fmul s18, s18, s31
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fmla s21, s22, v30.s[0]
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fmla s18, s19, v30.s[0]
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fmla s21, s23, v24.s[0]
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fmla s18, s20, v24.s[0]
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fadd s21, s25, s21 // a0
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fadd s18, s25, s18 // d0
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dup v30.4s, v21.s[0] // a0
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dup v31.4s, v18.s[0] // d0
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ldr w7, [x2, #0]
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ldr w8, [x2, #4]
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ldr w9, [x2, #8]
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ldr w10, [x2, #12]
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add x2, x2, #16
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uxtw x7, w7
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uxtw x8, w8
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uxtw x9, w9
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uxtw x10, w10
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ld1r {v11.8b}, [x4]
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mul x7, x7, x15
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mul x8, x8, x15
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mul x9, x9, x15
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mul x10, x10, x15
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add x7, x0, x7
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add x8, x0, x8
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add x9, x0, x9
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add x10,x0, x10
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ld1 {v0.16b}, [x7]
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ld1 {v8.16b}, [x8]
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ld1 {v15.16b}, [x9]
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ld1 {v22.16b}, [x10]
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sxtl v1.8h, v0.8b // v1: int16x8_t
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sxtl2 v2.8h, v0.16b
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sxtl v9.8h, v8.8b
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sxtl2 v10.8h, v8.16b
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sxtl v16.8h, v15.8b
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sxtl2 v17.8h, v15.16b
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sxtl v23.8h, v22.8b
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sxtl2 v24.8h, v22.16b
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ssubw v1.8h, v1.8h, v11.8b
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ssubw v2.8h, v2.8h, v11.8b
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ssubw v9.8h, v9.8h, v11.8b
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ssubw v10.8h, v10.8h, v11.8b
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ssubw v16.8h, v16.8h, v11.8b
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ssubw v17.8h, v17.8h, v11.8b
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ssubw v23.8h, v23.8h, v11.8b
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ssubw v24.8h, v24.8h, v11.8b
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sxtl v4.4s, v1.4h
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sxtl2 v5.4s, v1.8h
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sxtl v6.4s, v2.4h
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sxtl2 v7.4s, v2.8h
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sxtl v11.4s, v9.4h
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sxtl2 v12.4s, v9.8h
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sxtl v13.4s, v10.4h
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sxtl2 v14.4s, v10.8h
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sxtl v18.4s, v16.4h
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sxtl2 v19.4s, v16.8h
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sxtl v20.4s, v17.4h
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sxtl2 v21.4s, v17.8h
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sxtl v25.4s, v23.4h
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sxtl2 v26.4s, v23.8h
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sxtl v27.4s, v24.4h
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sxtl2 v28.4s, v24.8h
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scvtf v4.4s, v4.4s // A
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scvtf v5.4s, v5.4s
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scvtf v6.4s, v6.4s
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scvtf v7.4s, v7.4s
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scvtf v11.4s, v11.4s // B
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scvtf v12.4s, v12.4s
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scvtf v13.4s, v13.4s
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scvtf v14.4s, v14.4s
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scvtf v18.4s, v18.4s // C
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scvtf v19.4s, v19.4s
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scvtf v20.4s, v20.4s
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scvtf v21.4s, v21.4s
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scvtf v25.4s, v25.4s // D
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scvtf v26.4s, v26.4s
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scvtf v27.4s, v27.4s
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scvtf v28.4s, v28.4s
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fmul v4.4s, v4.4s, v30.s[0]
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fmul v5.4s, v5.4s, v30.s[0]
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fmul v6.4s, v6.4s, v30.s[0]
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fmul v7.4s, v7.4s, v30.s[0]
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fmla v4.4s, v11.4s, v3.s[0]
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fmla v5.4s, v12.4s, v3.s[0]
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fmla v6.4s, v13.4s, v3.s[0]
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fmla v7.4s, v14.4s, v3.s[0]
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fmla v4.4s, v18.4s, v29.s[0]
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fmla v5.4s, v19.4s, v29.s[0]
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fmla v6.4s, v20.4s, v29.s[0]
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fmla v7.4s, v21.4s, v29.s[0]
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fmla v4.4s, v25.4s, v31.s[0]
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fmla v5.4s, v26.4s, v31.s[0]
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fmla v6.4s, v27.4s, v31.s[0]
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fmla v7.4s, v28.4s, v31.s[0]
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st1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64
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sub x5, x5, #1
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cmp x5, #1
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bge L1Loop
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END:
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ldp d8, d9, [sp, #48]
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ldp d10, d11, [sp, #32]
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ldp d12, d13, [sp, #16]
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ldp d14, d15, [sp], #64
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ret
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#endif
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