wehub-resource-sync
137 lines
2.8 KiB
ArmAsm
137 lines
2.8 KiB
ArmAsm
// MNNCubicLineC16.S
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// MNN
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//
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// Created by MNN on 2019/01/18.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNCubicLineC16
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// void MNNCubicLineC16(int8_t* dst, const float* A, const float* B, const float* C, const float* D, float* t, int8_t* zeroPoint,
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// size_t number, ssize_t minValue, ssize_t maxValue);
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// Auto load:
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// x0: dst, x1: A, x2: B, x3: C, x4: D, x5: t, x6: zeroPoint, x7: number
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// Load from sp: x8: minValue, x9: maxValue
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ldr x8, [sp, #0]
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ldr x9, [sp, #8]
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stp d14, d15, [sp, #-64]!
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stp d12, d13, [sp, #16]
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stp d10, d11, [sp, #32]
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stp d8, d9, [sp, #48]
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cmp x7, #0
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beq END
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ldr w5, [x5, #0]
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fmov s1, #1.0
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ld1r {v0.8b}, [x6]
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dup v31.4s, w5 // v31: t
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fmov s30, #1.0
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fsub s30, s30, s31 // 1-t
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fmul s29, s31, s31 // t^2
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fmul s28, s30, s30 // (1-t)^2
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fmul s27, s31, s29 // t^3
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fmul s26, s28, s30 // (1-t)^3
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fmov s25, #-2.25
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fmov s24, #1.25
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fmul s27, s27, s24
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fmul s26, s26, s24
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fmla s27, s25, v29.s[0]
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fmla s26, s25, v28.s[0]
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fadd s27, s27, s1 // bo
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fadd s26, s26, s1 // c0
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dup v3.4s, v27.s[0] // b0
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dup v29.4s, v26.s[0] // c0
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fadd s23, s31, s1 // t_a
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fmul s22, s23, s23 // t_a^2
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fmul s21, s22, s23 // t_a^3
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fadd s20, s30, s1 // t_b
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fmul s19, s20, s20 // t_b^2
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fmul s18, s19, s20 // t_b^3
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fmov s31, #-0.75
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fmov s30, #3.75
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fmov s24, #-6.0
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fmov s25, #3.0
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fmul s21, s21, s31
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fmul s18, s18, s31
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fmla s21, s22, v30.s[0]
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fmla s18, s19, v30.s[0]
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fmla s21, s23, v24.s[0]
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fmla s18, s20, v24.s[0]
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fadd s21, s25, s21 // a0
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fadd s18, s25, s18 // d0
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dup v30.4s, v21.s[0] // a0
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dup v31.4s, v18.s[0] // d0
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L1Loop:
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ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64
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ld1 {v11.4s, v12.4s, v13.4s, v14.4s}, [x2], #64
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ld1 {v18.4s, v19.4s, v20.4s, v21.4s}, [x3], #64
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ld1 {v25.4s, v26.4s, v27.4s, v28.4s}, [x4], #64
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fmul v4.4s, v4.4s, v30.s[0]
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fmul v5.4s, v5.4s, v30.s[0]
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fmul v6.4s, v6.4s, v30.s[0]
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fmul v7.4s, v7.4s, v30.s[0]
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fmla v4.4s, v11.4s, v3.s[0]
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fmla v5.4s, v12.4s, v3.s[0]
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fmla v6.4s, v13.4s, v3.s[0]
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fmla v7.4s, v14.4s, v3.s[0]
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fmla v4.4s, v18.4s, v29.s[0]
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fmla v5.4s, v19.4s, v29.s[0]
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fmla v6.4s, v20.4s, v29.s[0]
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fmla v7.4s, v21.4s, v29.s[0]
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fmla v4.4s, v25.4s, v31.s[0]
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fmla v5.4s, v26.4s, v31.s[0]
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fmla v6.4s, v27.4s, v31.s[0]
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fmla v7.4s, v28.4s, v31.s[0]
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fcvtas v4.4s, v4.4s
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fcvtas v5.4s, v5.4s
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fcvtas v6.4s, v6.4s
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fcvtas v7.4s, v7.4s
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dup v18.16b, w8
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dup v19.16b, w9
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sqxtn v4.4h, v4.4s
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sqxtn2 v4.8h, v5.4s
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sqxtn v6.4h, v6.4s
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sqxtn2 v6.8h, v7.4s
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saddw v4.8h, v4.8h, v0.8b
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saddw v6.8h, v6.8h, v0.8b
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sqxtn v10.8b, v4.8h
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sqxtn2 v10.16b, v6.8h
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smin v10.16b, v10.16b, v19.16b
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smax v10.16b, v10.16b, v18.16b
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st1 {v10.16b}, [x0], #16
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sub x7, x7, #1
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cmp x7, #1
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bge L1Loop
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END:
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ldp d8, d9, [sp, #48]
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ldp d10, d11, [sp, #32]
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ldp d12, d13, [sp, #16]
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ldp d14, d15, [sp], #64
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ret
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#endif
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