wehub-resource-sync
297 lines
6.7 KiB
ArmAsm
297 lines
6.7 KiB
ArmAsm
//
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// MNNConvRunForLineDepthwise.S
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// MNN
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//
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// Created by MNN on 2019/02/04.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNConvRunForLineDepthwise
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//void MNNConvRunForLineDepthwise(float* dst, const float* src, const float* weight, size_t width, size_t src_w_setup,
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// size_t fw, size_t fh, size_t dilateX_step, size_t dilateY_step, size_t height, size_t srcHStep, size_t dstHStep)
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//Auto Load:
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//x0:dst, x1:src, x2:weight, x3:width, x4:src_w_setup, x5:fw, x6:fh, x7:dilate_x_step
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//Load From sp:
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//x8:dilate_y_step, x15: height, x10: srcHStep, x11:dstHStep
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ldr x8, [sp, #0]
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ldr x15, [sp, #8]
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ldr x10, [sp, #16]
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ldr x11, [sp, #24]
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ldr x12, [sp, #32]
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ldr x13, [sp, #40]
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stp d8, d9, [sp, #(-16 * 3)]!
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stp d10, d11, [sp, #(16 * 2)]
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stp x19, x20, [sp, #(16 * 1)]
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mov x9, #4
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mul x4, x9, x4
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mul x7, x9, x7
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mul x8, x9, x8
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mul x10, x9, x10
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mul x11, x9, x11
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ld1 {v8.4s}, [x12] // bias
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ld1r {v10.4s}, [x13], #4 // min
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ld1r {v11.4s}, [x13]
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//dilate_y_step -> dilate_y_step - fw*dilate_x_step
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mul x9, x5, x7
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sub x8, x8, x9
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.macro assign_bias x0, x1, x2, x3
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mov \x0\().16b, v8.16b
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mov \x1\().16b, v8.16b
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mov \x2\().16b, v8.16b
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mov \x3\().16b, v8.16b
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.endm
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.macro compare_min_max x0, x1, x2, x3, xmin, xmax
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fmax \x0\().4s, \x0\().4s, \xmin\().4s
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fmax \x1\().4s, \x1\().4s, \xmin\().4s
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fmax \x2\().4s, \x2\().4s, \xmin\().4s
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fmax \x3\().4s, \x3\().4s, \xmin\().4s
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fmin \x0\().4s, \x0\().4s, \xmax\().4s
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fmin \x1\().4s, \x1\().4s, \xmax\().4s
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fmin \x2\().4s, \x2\().4s, \xmax\().4s
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fmin \x3\().4s, \x3\().4s, \xmax\().4s
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.endm
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LoopDY:
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mov v4.d[0], x10
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mov v4.d[1], x11
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mov v5.d[0], x0
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mov v5.d[1], x1
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mov v6.d[0], x3
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L16:
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cmp x3, #16
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blt L8
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mov x12, #16
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mul x12, x4, x12
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L16Loop:
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assign_bias v16, v17, v18, v19
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assign_bias v20, v21, v22, v23
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assign_bias v24, v25, v26, v27
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assign_bias v28, v29, v30, v31
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L16LoopH:
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mov x10, x5
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L16LoopW:
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ld1 {v7.4s}, [x2], #16
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ld1 {v0.4s}, [x1], x4
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subs x10, x10, #1
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ld1 {v1.4s}, [x1], x4
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fmla v16.4s, v7.4s, v0.4s
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fmla v17.4s, v7.4s, v1.4s
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ld1 {v2.4s}, [x1], x4
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ld1 {v3.4s}, [x1], x4
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fmla v18.4s, v7.4s, v2.4s
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fmla v19.4s, v7.4s, v3.4s
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ld1 {v0.4s}, [x1], x4
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ld1 {v1.4s}, [x1], x4
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fmla v20.4s, v7.4s, v0.4s
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fmla v21.4s, v7.4s, v1.4s
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ld1 {v2.4s}, [x1], x4
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ld1 {v3.4s}, [x1], x4
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fmla v22.4s, v7.4s, v2.4s
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fmla v23.4s, v7.4s, v3.4s
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ld1 {v0.4s}, [x1], x4
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ld1 {v1.4s}, [x1], x4
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fmla v24.4s, v7.4s, v0.4s
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fmla v25.4s, v7.4s, v1.4s
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ld1 {v2.4s}, [x1], x4
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ld1 {v3.4s}, [x1], x4
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fmla v26.4s, v7.4s, v2.4s
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fmla v27.4s, v7.4s, v3.4s
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ld1 {v0.4s}, [x1], x4
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ld1 {v1.4s}, [x1], x4
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fmla v28.4s, v7.4s, v0.4s
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fmla v29.4s, v7.4s, v1.4s
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ld1 {v2.4s}, [x1], x4
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ld1 {v3.4s}, [x1], x4
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fmla v30.4s, v7.4s, v2.4s
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fmla v31.4s, v7.4s, v3.4s
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sub x1, x1, x12
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add x1, x1, x7
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bne L16LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L16LoopH
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sub x3, x3, #16
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compare_min_max v16, v17, v18, v19, v10, v11
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compare_min_max v20, v21, v22, v23, v10, v11
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compare_min_max v24, v25, v26, v27, v10, v11
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compare_min_max v28, v29, v30, v31, v10, v11
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st1 {v16.4s, v17.4s, v18.4s, v19.4s}, [x0], #64
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add x1, x13, x12
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cmp x3, #16
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mov x2, x14
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st1 {v20.4s, v21.4s, v22.4s, v23.4s}, [x0], #64
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st1 {v24.4s, v25.4s, v26.4s, v27.4s}, [x0], #64
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st1 {v28.4s, v29.4s, v30.4s, v31.4s}, [x0], #64
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bge L16Loop
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L8:
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cmp x3, #7
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ble L4
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mov x12, #8
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mul x12, x4, x12
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L8Loop:
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assign_bias v16, v17, v18, v19
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assign_bias v20, v21, v22, v23
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L8LoopH:
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mov x10, x5
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L8LoopW:
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ld1 {v3.4s}, [x2], #16
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ld1 {v0.4s}, [x1], x4
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subs x10, x10, #1
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fmla v16.4s, v3.4s, v0.4s
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ld1 {v1.4s}, [x1], x4
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fmla v17.4s, v3.4s, v1.4s
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ld1 {v0.4s}, [x1], x4
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fmla v18.4s, v0.4s, v3.4s
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ld1 {v1.4s}, [x1], x4
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fmla v19.4s, v1.4s, v3.4s
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ld1 {v0.4s}, [x1], x4
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fmla v20.4s, v0.4s, v3.4s
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ld1 {v1.4s}, [x1], x4
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fmla v21.4s, v1.4s, v3.4s
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ld1 {v0.4s}, [x1], x4
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fmla v22.4s, v0.4s, v3.4s
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ld1 {v1.4s}, [x1], x4
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fmla v23.4s, v1.4s, v3.4s
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sub x1, x1, x12
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add x1, x1, x7
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bne L8LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L8LoopH
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compare_min_max v16, v17, v18, v19, v10, v11
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compare_min_max v20, v21, v22, v23, v10, v11
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sub x3, x3, #8
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st1 {v16.4s, v17.4s, v18.4s, v19.4s}, [x0], #64
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add x1, x13, x12
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mov x2, x14
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st1 {v20.4s, v21.4s, v22.4s, v23.4s}, [x0], #64
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L4:
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cmp x3, #4
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ble L1
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mov x12, #4
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mul x12, x4, x12
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L4Loop:
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assign_bias v16, v17, v18, v19
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L4LoopH:
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mov x10, x5
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L4LoopW:
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ld1 {v3.4s}, [x2], #16
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ld1 {v0.4s}, [x1], x4
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subs x10, x10, #1
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fmla v16.4s, v3.4s, v0.4s
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ld1 {v1.4s}, [x1], x4
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fmla v17.4s, v3.4s, v1.4s
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ld1 {v0.4s}, [x1], x4
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fmla v18.4s, v0.4s, v3.4s
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ld1 {v1.4s}, [x1], x4
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fmla v19.4s, v1.4s, v3.4s
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sub x1, x1, x12
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add x1, x1, x7
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bne L4LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L4LoopH
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compare_min_max v16, v17, v18, v19, v10, v11
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sub x3, x3, #4
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st1 {v16.4s, v17.4s, v18.4s, v19.4s}, [x0], #64
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add x1, x13, x12
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mov x2, x14
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L1:
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cmp x3, #0
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beq End
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L1Loop:
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mov v0.16b, v8.16b
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mov x9, x6
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mov x11, x1
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mov x12, x2
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L1LoopH:
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mov x10, x5
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L1LoopW:
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ld1 {v1.4s}, [x1], x7
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ld1 {v2.4s}, [x2], #16
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fmla v0.4s, v1.4s, v2.4s
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subs x10, x10, #1
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bne L1LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L1LoopH
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subs x3, x3, #1
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fmax v0.4s, v0.4s, v10.4s
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fmin v0.4s, v0.4s, v11.4s
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st1 {v0.4s}, [x0], #16
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mov x2, x12
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add x1, x11, x4
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bne L1Loop
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End:
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mov x10, v4.d[0]
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mov x11, v4.d[1]
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mov x0, v5.d[0]
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mov x1, v5.d[1]
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mov x3, v6.d[0]
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subs x15, x15, #1
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add x0, x0, x11
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add x1, x1, x10
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bne LoopDY
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ldp x19, x20, [sp, #(16 * 1)]
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ldp d10, d11, [sp, #(16 * 2)]
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ldp d8, d9, [sp], #(16 * 3)
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ret
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//MNNConvRunForLineDepthwise End
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#endif
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