wehub-resource-sync
223 lines
4.6 KiB
ArmAsm
223 lines
4.6 KiB
ArmAsm
//
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// MNNConvRunForLineDepthWiseInt8.S
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// MNN
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//
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// Created by MNN on 2018/09/12.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNConvRunForLineDepthWiseInt8
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//void MNNConvRunForLineDepthWiseInt8(float* dst, const int8_t* src, const int8_t* weight, size_t width, size_t src_w_setup, size_t fw, size_t fh,
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//size_t dilate_x_step, size_t dilate_y_step, const float* alpha_z)
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//Auto Load:
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//x0:dst, x1:src, x2:weight, x3:width
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//x4:src_w_setup, x5:fw, x6:fh, x7:dilate_x_step
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//Load from sp:
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//x8:dilate_y_step, x9:alpha_z
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ldr x8, [sp, #0]
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ldr x9, [sp, #8]
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ld1 {v4.4s}, [x9]
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//dilate_y_step -> dilate_y_step - fw*dilate_x_step
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mul x9, x5, x7
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sub x8, x8, x9
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L8:
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cmp x3, #8
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blt L4
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mov x12, #8
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mul x12, x4, x12
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L8Loop:
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movi v16.4s, #0
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movi v17.4s, #0
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movi v18.4s, #0
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movi v19.4s, #0
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movi v20.4s, #0
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movi v21.4s, #0
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movi v22.4s, #0
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movi v23.4s, #0
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L8LoopH:
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mov x10, x5
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L8LoopW:
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ld1 {v3.s}[0], [x2], #4
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dup v3.2s, v3.s[0]
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sxtl v3.8h, v3.8b
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ld1 {v0.s}[0], [x1], x4
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ld1 {v0.s}[1], [x1], x4
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subs x10, x10, #1
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sxtl v1.8h, v0.8b
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ld1 {v0.s}[2], [x1], x4
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ld1 {v0.s}[3], [x1], x4
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sxtl2 v2.8h, v0.16b
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smlal v16.4s, v3.4h, v1.4h
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ld1 {v0.s}[0], [x1], x4
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smlal2 v17.4s, v3.8h, v1.8h
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ld1 {v0.s}[1], [x1], x4
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ld1 {v0.s}[2], [x1], x4
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ld1 {v0.s}[3], [x1], x4
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smlal v18.4s, v3.4h, v2.4h
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sxtl v1.8h, v0.8b
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smlal2 v19.4s, v3.8h, v2.8h
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sxtl2 v2.8h, v0.16b
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smlal v20.4s, v3.4h, v1.4h
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smlal2 v21.4s, v3.8h, v1.8h
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smlal v22.4s, v3.4h, v2.4h
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smlal2 v23.4s, v3.8h, v2.8h
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sub x1, x1, x12
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add x1, x1, x7
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bne L8LoopW
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L8LoopWEnd:
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subs x9, x9, #1
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add x1, x1, x8
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bne L8LoopH
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sub x3, x3, #8
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scvtf v16.4s, v16.4s
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scvtf v17.4s, v17.4s
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scvtf v18.4s, v18.4s
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fmul v16.4s, v16.4s, v4.4s
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fmul v17.4s, v17.4s, v4.4s
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scvtf v19.4s, v19.4s
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scvtf v20.4s, v20.4s
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st1 {v16.4s, v17.4s}, [x0], #32
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fmul v18.4s, v18.4s, v4.4s
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fmul v19.4s, v19.4s, v4.4s
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fmul v20.4s, v20.4s, v4.4s
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scvtf v21.4s, v21.4s
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st1 {v18.4s, v19.4s}, [x0], #32
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scvtf v22.4s, v22.4s
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scvtf v23.4s, v23.4s
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fmul v21.4s, v21.4s, v4.4s
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fmul v22.4s, v22.4s, v4.4s
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fmul v23.4s, v23.4s, v4.4s
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st1 {v20.4s, v21.4s}, [x0], #32
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mov x1, x13
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mov x2, x14
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add x1, x1, x12
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cmp x3, #8
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st1 {v22.4s, v23.4s}, [x0], #32
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bge L8Loop
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L4:
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cmp x3, #4
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blt L1
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mov x12, #4
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mul x12, x4, x12
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L4Loop:
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movi v16.4s, #0
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movi v17.4s, #0
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movi v18.4s, #0
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movi v19.4s, #0
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L4LoopH:
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mov x10, x5
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L4LoopW:
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ld1 {v3.s}[0], [x2], #4
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dup v3.2s, v3.s[0]
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sxtl v3.8h, v3.8b
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ld1 {v0.s}[0], [x1], x4
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ld1 {v0.s}[1], [x1], x4
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subs x10, x10, #1
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sxtl v1.8h, v0.8b
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ld1 {v0.s}[2], [x1], x4
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ld1 {v0.s}[3], [x1], x4
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sxtl2 v2.8h, v0.16b
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smlal v16.4s, v3.4h, v1.4h
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smlal2 v17.4s, v3.8h, v1.8h
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smlal v18.4s, v3.4h, v2.4h
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smlal2 v19.4s, v3.8h, v2.8h
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sub x1, x1, x12
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add x1, x1, x7
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bne L4LoopW
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L4LoopWEnd:
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subs x9, x9, #1
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add x1, x1, x8
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bne L4LoopH
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sub x3, x3, #4
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scvtf v16.4s, v16.4s
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scvtf v17.4s, v17.4s
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scvtf v18.4s, v18.4s
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fmul v16.4s, v16.4s, v4.4s
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fmul v17.4s, v17.4s, v4.4s
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scvtf v19.4s, v19.4s
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scvtf v20.4s, v20.4s
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st1 {v16.4s, v17.4s}, [x0], #32
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fmul v18.4s, v18.4s, v4.4s
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fmul v19.4s, v19.4s, v4.4s
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st1 {v18.4s, v19.4s}, [x0], #32
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mov x1, x13
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mov x2, x14
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add x1, x1, x12
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cmp x3, #4
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bge L4Loop
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L1:
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cmp x3, #0
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beq End
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L1Loop:
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movi v0.4s, #0
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mov x9, x6
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mov x11, x1
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mov x12, x2
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L1LoopH:
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mov x10, x5
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L1LoopW:
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ld1 {v1.s}[0], [x1], x7
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ld1 {v2.s}[0], [x2], #4
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sxtl v1.8h, v1.8b
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sxtl v2.8h, v2.8b
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smlal v0.4s, v1.4h, v2.4h
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subs x10, x10, #1
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bne L1LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L1LoopH
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subs x3, x3, #1
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scvtf v0.4s, v0.4s
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fmul v0.4s, v0.4s, v4.4s
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st1 {v0.4s}, [x0], #16
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mov x2, x12
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add x1, x11, x4
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bne L1Loop
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End:
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ret
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#endif
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