wehub-resource-sync
117 lines
2.8 KiB
ArmAsm
117 lines
2.8 KiB
ArmAsm
#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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// void MNNC3ToC4Fast(const unsigned char* source, unsigned char* dest, size_t count);
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asm_function MNNC3ToC4Fast
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// x0: source, x1: dest, x2: count
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stp d14, d15, [sp, #(-16 * 4)]!
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stp d12, d13, [sp, #(16 * 1)]
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stp d10, d11, [sp, #(16 * 2)]
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stp d8, d9, [sp, #(16 * 3)]
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movi v3.16b, #255
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movi v7.16b, #255
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movi v11.16b, #255
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movi v15.16b, #255
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movi v19.16b, #255
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movi v23.16b, #255
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movi v27.16b, #255
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movi v31.16b, #255
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L16:
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cmp x2, #16
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blt L12
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ld3 {v0.16b, v1.16b, v2.16b}, [x0], #48
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ld3 {v4.16b, v5.16b, v6.16b}, [x0], #48
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ld3 {v8.16b, v9.16b, v10.16b}, [x0], #48
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ld3 {v12.16b, v13.16b, v14.16b}, [x0], #48
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ld3 {v16.16b, v17.16b, v18.16b}, [x0], #48
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ld3 {v20.16b, v21.16b, v22.16b}, [x0], #48
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ld3 {v24.16b, v25.16b, v26.16b}, [x0], #48
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ld3 {v28.16b, v29.16b, v30.16b}, [x0], #48
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sub x2, x2, #16
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st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], #64
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st4 {v4.16b, v5.16b, v6.16b, v7.16b}, [x1], #64
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st4 {v8.16b, v9.16b, v10.16b, v11.16b}, [x1], #64
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st4 {v12.16b, v13.16b, v14.16b, v15.16b}, [x1], #64
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st4 {v16.16b, v17.16b, v18.16b, v19.16b}, [x1], #64
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st4 {v20.16b, v21.16b, v22.16b, v23.16b}, [x1], #64
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st4 {v24.16b, v25.16b, v26.16b, v27.16b}, [x1], #64
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st4 {v28.16b, v29.16b, v30.16b, v31.16b}, [x1], #64
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b L16
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L12:
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cmp x2, #12
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blt L8
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ld3 {v0.16b, v1.16b, v2.16b}, [x0], #48
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ld3 {v4.16b, v5.16b, v6.16b}, [x0], #48
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ld3 {v8.16b, v9.16b, v10.16b}, [x0], #48
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ld3 {v12.16b, v13.16b, v14.16b}, [x0], #48
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ld3 {v16.16b, v17.16b, v18.16b}, [x0], #48
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ld3 {v20.16b, v21.16b, v22.16b}, [x0], #48
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sub x2, x2, #12
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st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], #64
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st4 {v4.16b, v5.16b, v6.16b, v7.16b}, [x1], #64
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st4 {v8.16b, v9.16b, v10.16b, v11.16b}, [x1], #64
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st4 {v12.16b, v13.16b, v14.16b, v15.16b}, [x1], #64
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st4 {v16.16b, v17.16b, v18.16b, v19.16b}, [x1], #64
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st4 {v20.16b, v21.16b, v22.16b, v23.16b}, [x1], #64
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b L12
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L8:
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cmp x2, #8
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blt L4
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ld3 {v0.16b, v1.16b, v2.16b}, [x0], #48
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ld3 {v4.16b, v5.16b, v6.16b}, [x0], #48
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ld3 {v8.16b, v9.16b, v10.16b}, [x0], #48
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ld3 {v12.16b, v13.16b, v14.16b}, [x0], #48
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sub x2, x2, #8
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st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], #64
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st4 {v4.16b, v5.16b, v6.16b, v7.16b}, [x1], #64
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st4 {v8.16b, v9.16b, v10.16b, v11.16b}, [x1], #64
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st4 {v12.16b, v13.16b, v14.16b, v15.16b}, [x1], #64
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b L8
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L4:
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cmp x2, #4
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blt L2
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ld3 {v0.16b, v1.16b, v2.16b}, [x0], #48
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ld3 {v4.16b, v5.16b, v6.16b}, [x0], #48
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sub x2, x2, #4
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st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], #64
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st4 {v4.16b, v5.16b, v6.16b, v7.16b}, [x1], #64
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b L4
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L2:
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cmp x2, #2
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blt L1
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ld3 {v0.16b, v1.16b, v2.16b}, [x0], #48
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sub x2, x2, #2
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st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], #64
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b L2
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L1:
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cmp x2, #1
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blt End
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ld3 {v0.8b, v1.8b, v2.8b}, [x0], #24
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st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x1], #32
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End:
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ldp d8, d9, [sp, #(16 * 3)]
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ldp d10, d11, [sp, #(16 * 2)]
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ldp d12, d13, [sp, #(16 * 1)]
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ldp d14, d15, [sp], #(16 * 4)
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ret
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#endif
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