wehub-resource-sync
136 lines
3.1 KiB
ArmAsm
136 lines
3.1 KiB
ArmAsm
//
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// MNNTranspose16Bit8x8.S
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// MNN
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//
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// Created by MNN on 2023/11/09.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __arm__
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#ifndef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNTranspose16Bit8x8
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//void MNNTranspose16Bit8x8(int16_t* dstO, const int16_t* srcO, int* dim)
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//Auto: r0: dstO, r1:srcO, r2: dim
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push {r4-r8, lr} // avoid to touch platform-register r-9
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ldr r4, [r2, #0]
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ldr r5, [r2, #4]
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ldr r6, [r2, #8]
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ldr r7, [r2, #12]
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// r4, r5 -> wC8, hC8
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lsr r4, r4, #3
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lsr r5, r5, #3
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// r6, r7 -> srcStride * sizeof(half), dstStride * sizeof(half)
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lsl r6, r6, #1
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lsl r7, r7, #1
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LoopY:
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mov r2, r4
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mov r8, r0
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mov lr, r1
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LoopX:
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/*
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after vld1.16
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[ 0, 1, 2, 3, 4, 5, 6, 7]
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[ 8, 9, 10, 11, 12, 13, 14, 15]
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[16, 17, 18, 19, 20, 21, 22, 23]
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[24, 25, 26, 27, 28, 29, 30, 31]
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[32, 33, 34, 35, 36, 37, 38, 39]
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[40, 41, 42, 43, 44, 45, 46, 47]
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[48, 49, 50, 51, 52, 53, 54, 55]
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[56, 57, 58, 59, 60, 61, 62, 63]
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*/
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vld1.16 {q0}, [r1], r6
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vld1.16 {q1}, [r1], r6
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vld1.16 {q2}, [r1], r6
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vld1.16 {q3}, [r1], r6
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vld1.16 {q4}, [r1], r6
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vld1.16 {q5}, [r1], r6
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vld1.16 {q6}, [r1], r6
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vld1.16 {q7}, [r1], r6
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/*
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after vtrn.16
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[ 0, 8, 2, 10, 4, 12, 6, 14]
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[ 1, 9, 3, 11, 5, 13, 7, 15]
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[16, 24, 18, 26, 20, 28, 22, 30]
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[17, 25, 19, 27, 21, 29, 23, 31]
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[32, 40, 34, 42, 36, 44, 38, 46]
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[33, 41, 35, 43, 37, 45, 39, 47]
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[48, 56, 50, 58, 52, 60, 54, 62]
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[49, 57, 51, 59, 53, 61, 55, 63]
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*/
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vtrn.16 q0, q1
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vtrn.16 q2, q3
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vtrn.16 q4, q5
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vtrn.16 q6, q7
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/*
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after vtrn.32
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[ 0, 8, 16, 24, 4, 12, 20, 28]
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[ 1, 9, 17, 25, 5, 13, 21, 29]
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[ 2, 10, 18, 26, 6, 14, 22, 30]
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[ 3, 11, 19, 27, 7, 15, 23, 31]
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[32, 40, 48, 56, 36, 44, 52, 60]
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[33, 41, 49, 57, 37, 45, 53, 61]
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[34, 42, 50, 58, 38, 46, 54, 62]
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[35, 43, 51, 59, 39, 47, 55, 63]
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*/
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vtrn.32 q0, q2
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vtrn.32 q1, q3
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vtrn.32 q4, q6
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vtrn.32 q5, q7
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/*
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after vswp
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[ 0, 8, 16, 24, 32, 40, 48, 56]
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[ 1, 9, 17, 25, 33, 41, 49, 57]
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[ 2, 10, 18, 26, 34, 42, 50, 58]
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[ 3, 11, 19, 27, 35, 43, 51, 59]
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[ 4, 12, 20, 28, 36, 44, 52, 60]
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[ 5, 13, 21, 29, 37, 45, 53, 61]
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[ 6, 14, 22, 30, 38, 46, 54, 62]
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[ 7, 15, 23, 31, 39, 47, 55, 63]
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*/
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vswp d1, d8
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vswp d3, d10
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vswp d5, d12
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vswp d7, d14
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mov r12, r0
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vst1.16 {q0}, [r12], r7
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vst1.16 {q1}, [r12], r7
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vst1.16 {q2}, [r12], r7
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vst1.16 {q3}, [r12], r7
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vst1.16 {q4}, [r12], r7
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vst1.16 {q5}, [r12], r7
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vst1.16 {q6}, [r12], r7
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vst1.16 {q7}, [r12], r7
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add r0, r0, #16 // 4 * sizeof(float)
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subs r2, r2, #1
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bne LoopX
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lsl r12, r7, #3
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subs r5, r5, #1
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add r1, lr, #16 // 8 * sizeof(half)
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add r0, r8, r12
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bne LoopY
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End:
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pop {r4-r8, pc}
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#endif
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#endif
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