wehub-resource-sync
173 lines
3.3 KiB
ArmAsm
173 lines
3.3 KiB
ArmAsm
//
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// MNNScaleAndAddBiasInt8.S
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// MNN
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//
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// Created by MNN on 2019/02/04.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __arm__
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#ifndef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNScaleAndAddBiasInt8
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// MNNScaleAndAddBiasInt8(int8_t* dst, const int8_t* src, const int32_t* bias, const int32_t* alpha, int32_t mShiftBits,
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// ssize_t minValue, ssize_t maxValue, int8_t* inputZeroPoint, int8_t* outputZeroPoint, ssize_t planeNumber, ssize_t biasNumber, ssize_t pack)
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//Auto: r0:dst, r1:src, r2:bias, r3:alpha
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//Load from sp: r4:mShiftBits, r5:minValue, r6:maxValue, r7:inputZeroPoint, r12:outputZeroPoint, r8:planeNumber, r10:biasNumber
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push {r4-r8, r10-r12, lr}
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ldr r4, [sp, #36]
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ldr r5, [sp, #40]
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ldr r6, [sp, #44]
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ldr r7, [sp, #48]
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ldr r12, [sp, #52]
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ldr r8, [sp, #56]
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ldr r10, [sp, #60]
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vpush {q4-q7}
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vdup.s8 q7, r5
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vdup.s8 q8, r6
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vld1.8 {d24[0]}, [r7]
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vld1.8 {d26[0]}, [r12]
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vdup.8 d24, d24[0]
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vdup.8 d26, d26[0]
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cmp r8, #0
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beq BSEnd
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cmp r10, #0
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beq BSEnd
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BSLoopZ:
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mov r11, r8
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vld1.32 {q15}, [r2]!
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vld1.32 {q14}, [r3]!
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cmp r11, #2
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blt BSLoopP1
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cmp r11, #4
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blt BSLoopP2
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BSLoopP4:
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vld1.8 {q0}, [r1]! // q0: 4x(4xint8_t)
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vmovl.s8 q1, d0
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vmovl.s8 q2, d1
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vsubw.s8 q1, q1, d24
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vsubw.s8 q2, q2, d24
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vmovl.s16 q3, d2
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vmovl.s16 q4, d3
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vmovl.s16 q5, d4
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vmovl.s16 q6, d5
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vmul.s32 q3, q3, q14
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vmul.s32 q4, q4, q14
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vmul.s32 q5, q5, q14
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vmul.s32 q6, q6, q14
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vadd.s32 q3, q3, q15
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vadd.s32 q4, q4, q15
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vadd.s32 q5, q5, q15
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vadd.s32 q6, q6, q15
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vrshrn.s32 d6, q3, #15
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vrshrn.s32 d7, q4, #15
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vrshrn.s32 d10, q5, #15
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vrshrn.s32 d11, q6, #15
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vaddw.s8 q3, q3, d26
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vaddw.s8 q5, q5, d26
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vqmovn.s16 d6, q3
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vqmovn.s16 d7, q5
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vmax.s8 q3, q3, q7
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vmin.s8 q3, q3, q8
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vst1.s8 {q3}, [r0]!
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sub r11, r11, #4
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cmp r11, #4
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bge BSLoopP4
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cmp r11, #0
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beq BSLoopPEnd
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cmp r11, #2
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blt BSLoopP1
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BSLoopP2:
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vld1.8 {d0}, [r1]! // q0: 2x(4xint8_t)
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//vsub.s8 d0, d0, d24
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vmovl.s8 q1, d0
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vsubw.s8 q1, q1, d24
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vmovl.s16 q3, d2
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vmovl.s16 q4, d3
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vmul.s32 q3, q3, q14
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vmul.s32 q4, q4, q14
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vadd.s32 q3, q3, q15
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vadd.s32 q4, q4, q15
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vrshrn.s32 d6, q3, #15
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vrshrn.s32 d7, q4, #15
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vaddw.s8 q3, q3, d26
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vqmovn.s16 d6, q3
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vmax.s8 d6, d6, d14
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vmin.s8 d6, d6, d16
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vst1.s8 {d6}, [r0]!
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sub r11, r11, #2
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cmp r11, #2
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bge BSLoopP2
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cmp r11, #0
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beq BSLoopPEnd
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BSLoopP1:
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ldr lr, [r1], #4
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vdup.32 d0, lr
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vmovl.s8 q1, d0
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vsubw.s8 q1, q1, d24
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vmovl.s16 q3, d2
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vmul.s32 q3, q3, q14
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vadd.s32 q3, q3, q15
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vrshrn.s32 d6, q3, #15
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vmov.32 d7, d6
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vaddw.s8 q3, q3, d26
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vqmovn.s16 d6, q3
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vmax.s8 d6, d6, d14
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vmin.s8 d6, d6, d16
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vst1.32 {d6[0]}, [r0]!
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sub r11, r11, #1
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cmp r11, #1
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bge BSLoopP1
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BSLoopPEnd:
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subs r10, r10, #1
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bne BSLoopZ
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BSEnd:
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vpop {q4-q7}
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pop {r4-r8, r10-r12, pc}
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#endif
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#endif
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