wehub-resource-sync
146 lines
2.3 KiB
ArmAsm
146 lines
2.3 KiB
ArmAsm
//
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// MNNSamplerC4NearestOpt.S
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// MNN
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//
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// Created by MNN on 2018/12/19.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __arm__
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#ifndef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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//void MNNSamplerC4NearestOpt(const unsigned char* source, unsigned char* dest, float* points, size_t count, size_t iw, size_t ih, size_t yStride);
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asm_function MNNSamplerC4NearestOpt
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//Auto: r0:source, r1:dest, r2:points, r3:count
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//Load: r4: xMax, r5: yMax, r6:yStride
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push {r4-r8, r10, r11, lr} // avoid to touch platform-register r-9
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ldr r4, [sp, #32]
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ldr r5, [sp, #36]
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vdup.32 q12, r4
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vdup.32 q13, r5
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vmov.i32 q11, #0
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vmov.i32 q10, #4
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ldr r6, [sp, #40]
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vld1.32 {q0}, [r2]
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L8:
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cmp r3, #8
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blt L1
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vdup.32 q15, r6
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vdup.32 q14, r0
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L8Loop:
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vcvtr.s32.f32 s8, s0
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vcvtr.s32.f32 s12, s1
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vadd.f32 d3, d0, d1
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vcvtr.s32.f32 s9, s6
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vcvtr.s32.f32 s13, s7
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vadd.f32 d0, d3, d1
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vcvtr.s32.f32 s10, s0
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vcvtr.s32.f32 s14, s1
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vadd.f32 d3, d0, d1
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vcvtr.s32.f32 s11, s6
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vcvtr.s32.f32 s15, s7
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vmax.s32 q2, q2, q11
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vmax.s32 q3, q3, q11
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vmin.s32 q2, q2, q12
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vmin.s32 q3, q3, q13
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vmul.s32 q2, q2, q10
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vadd.f32 d0, d3, d1
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vmla.s32 q2, q15, q3
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vadd.s32 q2, q2, q14
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vmov.i32 r4, d4[0]
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vmov.i32 r5, d4[1]
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vld1.32 {d16[0]}, [r4]
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vcvtr.s32.f32 s8, s0
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vld1.32 {d16[1]}, [r5]
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vmov.i32 r4, d5[0]
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vmov.i32 r5, d5[1]
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vld1.32 {d17[0]}, [r4]
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vcvtr.s32.f32 s12, s1
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vld1.32 {d17[1]}, [r5]
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vadd.f32 d3, d0, d1
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vst1.32 {q8}, [r1]!
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vcvtr.s32.f32 s9, s6
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vcvtr.s32.f32 s13, s7
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vadd.f32 d0, d3, d1
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vcvtr.s32.f32 s10, s0
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vcvtr.s32.f32 s14, s1
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vadd.f32 d3, d0, d1
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vcvtr.s32.f32 s11, s6
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vcvtr.s32.f32 s15, s7
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vadd.f32 d0, d3, d1
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vmax.s32 q2, q2, q11
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vmax.s32 q3, q3, q11
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vmin.s32 q2, q2, q12
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vmin.s32 q3, q3, q13
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vmul.s32 q2, q2, q10
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vmla.s32 q2, q15, q3
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vadd.s32 q2, q2, q14
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vmov.i32 r4, d4[0]
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vmov.i32 r5, d4[1]
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vld1.32 {d16[0]}, [r4]
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vld1.32 {d16[1]}, [r5]
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vmov.i32 r4, d5[0]
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vmov.i32 r5, d5[1]
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vld1.32 {d17[0]}, [r4]
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vld1.32 {d17[1]}, [r5]
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vst1.32 {q8}, [r1]!
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sub r3, r3, #8
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cmp r3, #8
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bge L8Loop
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L1:
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cmp r3, #0
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mov r12, #4
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beq End
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L1Loop:
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vcvtr.s32.f32 s4, s0
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vcvtr.s32.f32 s6, s1
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vmax.s32 d2, d2, d22
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vmax.s32 d3, d3, d22
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vmin.s32 d2, d2, d24
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vmin.s32 d3, d3, d26
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vmov.i32 r4, d2[0]
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vmov.i32 r5, d3[0]
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mul r4, r4, r12
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add r4, r4, r0
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mul r5, r5, r6
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add r4, r4, r5
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vld1.32 {d3[0]}, [r4]
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vadd.f32 d0, d0, d1
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vst1.32 {d3[0]}, [r1]!
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subs r3, r3, #1
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bne L1Loop
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End:
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pop {r4-r8, r10, r11, pc}
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#endif
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#endif
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