wehub-resource-sync
154 lines
3.2 KiB
ArmAsm
154 lines
3.2 KiB
ArmAsm
//
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// MNNLineDepthWiseInt8AddBiasScaleUnit.S
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// MNN
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//
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// Created by MNN on 2019/06/05.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __arm__
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#ifndef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNLineDepthWiseInt8AddBiasScaleUnit
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//void MNNLineDepthWiseInt8AddBiasScaleUnit(int8_t* dst, const int8_t* src, const int8_t* weight, const QuanPostTreatParameters* parameters,
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// size_t width, size_t src_w_step, size_t fw, size_t fh, size_t dilateX_step,
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// size_t dilateY_step) {
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//struct QuanPostTreatParameters {
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// const float* scale;
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// const int32_t* bias;
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// int32_t maxValue;
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// int32_t minValue;
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// float roundValuePos = 0.5f;
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// float roundValueNeg = -0.5f;
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//};
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// Auto Load:
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// r0: dst*, r1: src*, r2: weight*, r3: parameters*
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// Load from sp
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// r4: width, r5: src_w_step, r6: fw, r7: fh, r8: dilateX_step, lr: dilateY_step, r10: scale_z, r11: mode
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push {r4-r8, r10, r11, lr} // avoid to touch platform-register r-9
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ldr r4, [sp, #32]
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ldr r5, [sp, #36]
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ldr r6, [sp, #40]
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ldr r7, [sp, #44]
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ldr r8, [sp, #48]
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ldr lr, [sp, #52]
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vpush {q4-q7}
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ldr r10, [r3, #0]
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vld1.32 {q12, q13}, [r10]! // scale, pack=16
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vld1.32 {q14, q15}, [r10]!
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ldr r11, [r3, #8]
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// d23: max, d22: min
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vdup.i8 d23, r11
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ldr r11, [r3, #12]
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vdup.i8 d22, r11
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ldr r3, [r3, #44] // bias
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mul r10, r6, r8
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sub lr, lr, r10
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L1:
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cmp r4, #0
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beq End
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L1Loop:
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vld1.32 {q7, q8}, [r3]!
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vld1.32 {q9, q10}, [r3]
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sub r3, r3, #32
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vmov.i32 d12[0], r1
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vmov.i32 d12[1], r2
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mov r10, r7
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L1LoopH:
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mov r11, r6
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L1LoopW:
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vld1.32 {q1}, [r2]!
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vld1.32 {q0}, [r1], r8
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vmovl.s8 q2, d0
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vmovl.s8 q3, d1
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vmovl.s8 q4, d2
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vmovl.s8 q5, d3
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vmlal.s16 q7, d4, d8
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vmlal.s16 q8, d5, d9
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vmlal.s16 q9, d6, d10
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vmlal.s16 q10, d7, d11
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subs r11, r11, #1
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bne L1LoopW
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L1LoopWEnd:
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subs r10, r10, #1
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add r1, r1, lr
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bne L1LoopH
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vmov.f32 q0, #0.5
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vmov.f32 q1, #-0.5
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vcvt.f32.s32 q7, q7
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vcvt.f32.s32 q8, q8
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vcvt.f32.s32 q9, q9
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vcvt.f32.s32 q10, q10
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vmul.f32 q7, q7, q12
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vmul.f32 q8, q8, q13
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vmul.f32 q9, q9, q14
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vmul.f32 q10, q10, q15
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/*
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vrshrn.s32 d14, q7, #14
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vrshrn.s32 d15, q8, #14
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vrshrn.s32 d18, q9, #14
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vrshrn.s32 d19, q10, #14
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*/
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.macro ROUND_TWO x0, x1
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vcgt.f32 q2, \x0, #0
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vcgt.f32 q3, \x1, #0
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vbsl.f32 q2, q0, q1
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vbsl.f32 q3, q0, q1
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vadd.f32 \x0, q2, \x0
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vadd.f32 \x1, q3, \x1
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vcvt.s32.f32 \x0, \x0
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vcvt.s32.f32 \x1, \x1
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.endm
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ROUND_TWO q7, q8
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ROUND_TWO q9, q10
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vqmovn.s32 d14, q7
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vqmovn.s32 d15, q8
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vqmovn.s32 d18, q9
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vqmovn.s32 d19, q10
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vqmovn.s16 d14, q7
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vqmovn.s16 d15, q9
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vmin.s8 d14, d14, d23
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vmax.s8 d14, d14, d22
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vmin.s8 d15, d15, d23
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vmax.s8 d15, d15, d22
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vst1.32 {q7}, [r0]!
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vmov.i32 r1, d12[0]
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vmov.i32 r2, d12[1]
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add r1, r1, r5
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subs r4, r4, #1
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bne L1Loop
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End:
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vpop {q4-q7}
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pop {r4-r8, r10, r11, pc}
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#endif
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#endif
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