wehub-resource-sync
199 lines
3.5 KiB
ArmAsm
199 lines
3.5 KiB
ArmAsm
//
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// MNNBinaryMaxInt8.S
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// MNN
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//
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// Created by MNN on 2019/08/15.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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/*
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struct QuanPrePostParameters{
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float* inputScale;
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float* outputScale;
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ssize_t* inputZeroPoint;
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ssize_t* outputZeroPoint;
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ssize_t minValue;
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ssize_t maxValue;
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};
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*/
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#ifdef __arm__
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#ifndef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNBinaryMaxInt8
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// MNNBinaryMaxInt8(int8_t* outputRaw, const int8_t* inputRaw0, const int8_t* inputRaw1, ssize_t* inputScalesInt32,
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// float* inputScalesFp32, const QuanPrePostParameters* params, size_t elementSize, size_t needBroadcast);
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// Auto load:
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// r0: dst, r1:src0, r2:src1, r3:quantScalesInt32
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// Load from sp:
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// r4:quantScalesFp32, r5: params, r6: size, r7: needBroadcast
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push {r4-r8, r10, r11, lr}
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ldr r4, [sp, #32]
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ldr r5, [sp, #36]
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ldr r6, [sp, #40]
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ldr r7, [sp, #44]
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vpush {q4-q7}
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ldr r12, [r3]
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vdup.s32 q13, r12 // scale
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ldr r4, [r3, #4]
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vdup.s32 q14, r4
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ldr lr, [r5, #8]
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ldr r8, [lr, #0]
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ldr r10,[lr, #4]
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ldr r3, [r5, #16] // minValue
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ldr r11, [r5, #20] // maxValue
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ldr r5, [r5, #12]
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ldr r5, [r5, #0]
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vdup.s8 d0, r8
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vdup.s8 d1, r10
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vdup.s8 d4, r5
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L4:
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cmp r6, #4
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blt L1
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L4Loop:
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cmp r7, #0
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beq L4NeedBroadcast0
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cmp r7, #1
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beq L4NeedBroadcast1
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L4NotNeedBroadcast:
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vld1.32 {q11}, [r1]!
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vld1.32 {q12}, [r2]!
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b L4Compute
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L4NeedBroadcast0:
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vld1.8 {d22[0]}, [r1]
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vdup.s8 q11, d22[0]
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vld1.32 {q12}, [r2]!
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b L4Compute
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L4NeedBroadcast1:
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vld1.32 {q11}, [r1]!
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vld1.8 {d24[0]}, [r2]
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vdup.s8 q12, d24[0]
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b L4Compute
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L4Compute:
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sub r6, r6, #4
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vmovl.s8 q4, d22
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vmovl.s8 q5, d23
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vmovl.s8 q6, d24
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vmovl.s8 q7, d25
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vsubw.s8 q4, q4, d0
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vsubw.s8 q5, q5, d0
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vsubw.s8 q6, q6, d1
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vsubw.s8 q7, q7, d1
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vmovl.s16 q8, d8
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vmovl.s16 q9, d9
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vmovl.s16 q10, d10
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vmovl.s16 q11, d11
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vmovl.s16 q3, d12
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vmovl.s16 q12, d13
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vmovl.s16 q15, d14
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vmovl.s16 q4, d15
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vmulq.s32 q8, q8, q13
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vmulq.s32 q9, q9, q13
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vmulq.s32 q10, q10, q13
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vmulq.s32 q11, q11, q13
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vmulq.s32 q3, q3, q14
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vmulq.s32 q12, q12, q14
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vmulq.s32 q15, q15, q14
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vmulq.s32 q4, q4, q14
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vmax.s32 q8, q8, q3
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vmax.s32 q9, q9, q12
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vmax.s32 q10, q10, q15
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vmax.s32 q11, q11, q4
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vdup.8 q12, r3
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vdup.8 q15, r11
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vqshrn.s32 d6, q8, #16
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vqshrn.s32 d7, q9, #16
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vqshrn.s32 d8, q10, #16
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vqshrn.s32 d9, q11, #16
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vaddw.s8 q3, q3, d4
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vaddw.s8 q4, q4, d4
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vqmovn.s16 d12, q3
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vqmovn.s16 d13, q4
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vmax.s8 q6, q6, q12
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vmin.s8 q6, q6, q15
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cmp r6, #4
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vst1.32 {q6}, [r0]!
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bge L4Loop
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L1:
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cmp r6, #0
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beq End
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vdup.8 d20, r3
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vdup.8 d22, r11
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L1Loop:
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cmp r7, #0
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beq L1NeedBroadcast0
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cmp r7, #1
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beq L1NeedBroadcast1
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L1NotNeedBroadcast:
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vld1.32 {d6[0]}, [r1]!
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vld1.32 {d8[0]}, [r2]!
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b L1Compute
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L1NeedBroadcast0:
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vld1.8 {d6[0]}, [r1]
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vdup.s8 d6, d6[0]
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vld1.32 {d8[0]}, [r2]!
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b L1Compute
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L1NeedBroadcast1:
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vld1.32 {d6[0]}, [r1]!
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vld1.8 {d8[0]}, [r2]
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vdup.s8 d8, d8[0]
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b L1Compute
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L1Compute:
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subs r6, r6, #1
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vmovl.s8 q3, d6
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vsubw.s8 q3, q3, d0
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vmovl.s16 q3, d6
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vmulq.s32 q3, q3, q13
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vmovl.s8 q5, d8
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vsubw.s8 q5, q5, d1
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vmovl.s16 q6, d10
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vmulq.s32 q6, q6, q14
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vmax.s32 q3, q3, q6
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vqshrn.s32 d6, q3, #16
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vaddw.s8 q3, q3, d4
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vqmovn.s16 d6, q3
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vmax.s8 d6, d6, d20
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vmin.s8 d6, d6, d22
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vst1.32 {d6[0]}, [r0]!
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bne L1Loop
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End:
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vpop {q4-q7}
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pop {r4-r8, r10, r11, pc}
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#endif
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#endif
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