wehub-resource-sync
128 lines
4.4 KiB
C++
128 lines
4.4 KiB
C++
//
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// CPUConvolution.hpp
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// MNN
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//
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// Created by MNN on 2018/07/15.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifndef CPUConvolution_hpp
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#define CPUConvolution_hpp
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#include <mutex>
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#include "CPUBackend.hpp"
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#include "core/ConvolutionCommon.hpp"
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namespace MNN {
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class PerfConfig {
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public:
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PerfConfig() : isParallelInner{false}, eTile{1}, ePack{1}, hPack{1}, instructionCosts{.0f} {}
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PerfConfig(bool isParallelInner_, int eTile_, int ePack_, int hPack_, float instructionCosts_)
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: isParallelInner{isParallelInner_},
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eTile{eTile_},
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ePack{ePack_},
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hPack{hPack_},
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instructionCosts{instructionCosts_} {}
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bool operator!=(const PerfConfig& other) {
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return isParallelInner != other.isParallelInner || ePack != other.ePack || eTile != other.eTile ||
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hPack != other.hPack;
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}
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PerfConfig& operator=(const PerfConfig& other) {
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isParallelInner = other.isParallelInner;
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ePack = other.ePack;
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eTile = other.eTile;
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hPack = other.hPack;
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instructionCosts = other.instructionCosts;
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return *this;
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}
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bool isParallelInner; // inner or outer parallel
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int eTile; // L2 cache tiling
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int ePack; // micro tile size along ow*oh dimension
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int hPack;
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float instructionCosts;
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};
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class CPUConvolution : public Execution {
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public:
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struct ResourceDequantizeInfo {
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int bits = 32;
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std::shared_ptr<Tensor> mScaleBias;
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};
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struct Resource {
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std::shared_ptr<Tensor> mWeight;
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std::shared_ptr<Tensor> mBias;
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ResourceDequantizeInfo mDequantize;
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Backend* backend;
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static void copyBias(float* dst, const float* bias, int outputCount, Backend* backend);
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bool copyBiasAlign(const float* bias, int outputCount);
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int hU;
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int lU;
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int lP;
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int hP;
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std::vector<float> mReluThreshold;
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};
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struct ResourceInt8 {
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std::vector<int> mInt8WeightKernelSum; // PTQ's sum, DynamicQ not use
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std::shared_ptr<Tensor> mWeightInt8; // PTQ's and DynamicQ's weight
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std::shared_ptr<Tensor> mOriginBias; // PTQ's and DynamicQ's bias
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std::shared_ptr<Tensor> mOriginScale; // PTQ's scale + bias, DynamicQ's alpha + zero;
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std::shared_ptr<Tensor> mWeightKernelSum; // PTQ's and DynamicQ's weight kernel sum;
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std::vector<float> mReluThreshold;
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// relu or relu6
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bool mRelu;
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int mWeightBits; // quant bits
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bool mUseConvQuan = true;
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bool mWeightAsymmetricQuant = true;
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// Origin Attributes from net
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float mInputScale = 0.0f;
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float mOutputScale = 0.0f;
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int32_t mInputZeroPoint;
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int32_t mOutputZeroPoint;
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int8_t mClampMin;
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int8_t mClampMax;
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bool mDynamicQuant = false;
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int32_t mBlockNum = 1;
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int32_t mHp = 0;
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int32_t mLp = 0;
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// For int4: 0: (x + half, x) -> int8, 1: (x, x + 1) -> int8.
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int32_t mPackMode = 0;
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};
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struct MutableResourceInt8 {
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MutableResourceInt8(std::shared_ptr<ResourceInt8> res, Backend* backend, float* scalePtr = nullptr);
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void updateInputOutputScale(std::vector<float> inputQuantInfo, std::vector<float> outputQuantInfo);
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std::shared_ptr<ResourceInt8> mResource;
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float mInputScale = 0.0f;
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float mOutputScale = 0.0f;
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int32_t mInputZeroPoint;
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int32_t mOutputZeroPoint;
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int8_t mClampMin;
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int8_t mClampMax;
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std::shared_ptr<Tensor> mBiasInt32;
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std::shared_ptr<Tensor> mScaleFloat;
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std::shared_ptr<Tensor> mBiasFloat;
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int32_t mShiftBits = 14;
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bool mValid;
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};
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static std::shared_ptr<ResourceInt8> makeResourceInt8(Backend* backend, const MNN::Op* op, int pack = 4);
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CPUConvolution(const Convolution2DCommon* convOp, Backend* b);
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virtual ~CPUConvolution() = default;
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virtual ErrorCode onResize(const std::vector<Tensor*>& inputs, const std::vector<Tensor*>& outputs) override;
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static int reorderWeightSize(int depth, int outputCount, int kernelSize, int unitDepth, int unitOC);
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std::vector<float> getPostParameters() const;
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public:
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PerfConfig mConvPerfconfig;
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protected:
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const Convolution2DCommon* mCommon;
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// In execute, use pad from mPadX and mPadY, don't use mCommon's pad
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mutable int mPadX;
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mutable int mPadY;
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};
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} // namespace MNN
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#endif /* CPUConvolution_hpp */
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