wehub-resource-sync
291 lines
6.9 KiB
ArmAsm
291 lines
6.9 KiB
ArmAsm
//
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// MNNDepthwiseConvFastKernelFP16.S
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// MNN
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//
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// Created by MNN on 2024/09/18.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNDepthwiseConvFastKernelFP16
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// void MNNDepthwiseConvFastKernelFP16(float* dst, const float* src, const float* weight, size_t width, size_t src_w_setup,
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// size_t fw, size_t fh, size_t dilateX_step, size_t dilateY_step, size_t height,
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// size_t srcHStep, size_t dstHStep, const float* bias, const float* parameters);
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//Auto Load:
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//x0:dst, x1:src, x2:weight, x3:width, x4:src_w_step=pack*1, x5:fw, x6:fh, x7:dilate_x_step
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//Load From sp:
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//x8:dilate_y_step, x15: height, x10: srcHStep, x11:dstHStep, x12:bias, x13: minmax
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ldr x8, [sp, #0]
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ldr x15, [sp, #8]
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ldr x10, [sp, #16]
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ldr x11, [sp, #24]
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ldr x12, [sp, #32]
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ldr x13, [sp, #40]
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stp d14, d15, [sp, #(-16 * 9)]!
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stp d12, d13, [sp, #(16 * 1)]
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stp d10, d11, [sp, #(16 * 2)]
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stp d8, d9, [sp, #(16 * 3)]
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stp x21, x22, [sp, #(16 * 4)]
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stp x19, x20, [sp, #(16 * 5)]
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stp x27, x28, [sp, #(16 * 6)]
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stp x25, x26, [sp, #(16 * 7)]
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stp x23, x24, [sp, #(16 * 8)]
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lsl x4, x4, #1 // src_w_step*sizeof(float)
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lsl x7, x7, #1 // dilate_x_step*sizeof(float)
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lsl x8, x8, #1 // dilate_y_step*sizeof(float)
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lsl x23, x10, #1 // srcHStep*sizeof(float)
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lsl x24, x11, #1 // dstHStep*sizeof(float)
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mov x20, x12 // bias
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mov x26, x13 // min
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add x27, x13, #2 // max
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//dilate_y_step -> dilate_y_step - fw*dilate_x_step
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mul x9, x5, x7
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sub x8, x8, x9
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mov x25, x3 // width
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.macro assign_bias x0, x1, x2, x3, bv
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mov \x0\().16b, \bv\().16b
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mov \x1\().16b, \bv\().16b
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mov \x2\().16b, \bv\().16b
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mov \x3\().16b, \bv\().16b
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.endm
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.macro compare_min_max x0, x1, x2, x3, xmin, xmax
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fmax \x0\().8h, \x0\().8h, \xmin\().8h
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fmax \x1\().8h, \x1\().8h, \xmin\().8h
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fmax \x2\().8h, \x2\().8h, \xmin\().8h
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fmax \x3\().8h, \x3\().8h, \xmin\().8h
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fmin \x0\().8h, \x0\().8h, \xmax\().8h
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fmin \x1\().8h, \x1\().8h, \xmax\().8h
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fmin \x2\().8h, \x2\().8h, \xmax\().8h
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fmin \x3\().8h, \x3\().8h, \xmax\().8h
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.endm
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LoopDY:
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//mov x23, x10
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//mov x24, x11
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mov x21, x0
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mov x22, x1
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L16:
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cmp x3, #16
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blt L8
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mov x12, #-176
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mov x19, #256
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L16Loop:
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ld1 {v8.8h}, [x20] // load bias
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assign_bias v16, v17, v18, v19, v8
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assign_bias v20, v21, v22, v23, v8
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assign_bias v24, v25, v26, v27, v8
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assign_bias v28, v29, v30, v31, v8
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L16LoopH:
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mov x10, x5
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L16LoopW:
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ld1 {v8.8h}, [x2], #16
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ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [x1], #64
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ld1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x1], #64
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ld1 {v9.8h, v10.8h, v11.8h, v12.8h}, [x1], #64
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subs x10, x10, #1
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fmla v16.8h, v8.8h, v0.8h
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fmla v17.8h, v8.8h, v1.8h
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fmla v18.8h, v8.8h, v2.8h
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fmla v19.8h, v8.8h, v3.8h
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fmla v20.8h, v8.8h, v4.8h
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fmla v21.8h, v8.8h, v5.8h
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fmla v22.8h, v8.8h, v6.8h
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fmla v23.8h, v8.8h, v7.8h
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ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [x1], x12
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fmla v24.8h, v8.8h, v9.8h
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fmla v25.8h, v8.8h, v10.8h
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fmla v26.8h, v8.8h, v11.8h
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fmla v27.8h, v8.8h, v12.8h
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fmla v28.8h, v8.8h, v0.8h
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fmla v29.8h, v8.8h, v1.8h
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fmla v30.8h, v8.8h, v2.8h
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fmla v31.8h, v8.8h, v3.8h
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bne L16LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L16LoopH
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ld1r {v10.8h}, [x26] // min
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ld1r {v11.8h}, [x27] // max
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sub x3, x3, #16
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compare_min_max v16, v17, v18, v19, v10, v11
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compare_min_max v20, v21, v22, v23, v10, v11
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compare_min_max v24, v25, v26, v27, v10, v11
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compare_min_max v28, v29, v30, v31, v10, v11
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st1 {v16.8h, v17.8h, v18.8h, v19.8h}, [x0], #64
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add x1, x13, x19 // 16 * pack * sizeof(float)
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cmp x3, #16
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mov x2, x14
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st1 {v20.8h, v21.8h, v22.8h, v23.8h}, [x0], #64
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st1 {v24.8h, v25.8h, v26.8h, v27.8h}, [x0], #64
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st1 {v28.8h, v29.8h, v30.8h, v31.8h}, [x0], #64
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bge L16Loop
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L8:
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ld1r {v10.8h}, [x26] // min
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ld1r {v11.8h}, [x27] // max
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ld1 {v24.8h}, [x20] // load bias
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cmp x3, #7
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ble L4
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mov x12, #-48
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mov x19, #128
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L8Loop:
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assign_bias v16, v17, v18, v19, v24
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assign_bias v20, v21, v22, v23, v24
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L8LoopH:
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mov x10, x5
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L8LoopW:
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ld1 {v8.8h}, [x2], #16
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ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [x1], #64
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ld1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x1], x12
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subs x10, x10, #1
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fmla v16.8h, v8.8h, v0.8h
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fmla v17.8h, v8.8h, v1.8h
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fmla v18.8h, v8.8h, v2.8h
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fmla v19.8h, v8.8h, v3.8h
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fmla v20.8h, v8.8h, v4.8h
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fmla v21.8h, v8.8h, v5.8h
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fmla v22.8h, v8.8h, v6.8h
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fmla v23.8h, v8.8h, v7.8h
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bne L8LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L8LoopH
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compare_min_max v16, v17, v18, v19, v10, v11
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compare_min_max v20, v21, v22, v23, v10, v11
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sub x3, x3, #8
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st1 {v16.8h, v17.8h, v18.8h, v19.8h}, [x0], #64
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add x1, x13, x19 // 8 * pack * sizeof(float)
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mov x2, x14
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st1 {v20.8h, v21.8h, v22.8h, v23.8h}, [x0], #64
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L4:
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cmp x3, #4
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ble L1
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mov x12, #16
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mov x19, #64
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L4Loop:
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assign_bias v16, v17, v18, v19, v24
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L4LoopH:
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mov x10, x5
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L4LoopW:
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ld1 {v8.8h}, [x2], #16
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ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [x1], x12
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subs x10, x10, #1
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fmla v16.8h, v8.8h, v0.8h
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fmla v17.8h, v8.8h, v1.8h
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fmla v18.8h, v8.8h, v2.8h
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fmla v19.8h, v8.8h, v3.8h
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bne L4LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L4LoopH
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compare_min_max v16, v17, v18, v19, v10, v11
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sub x3, x3, #4
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st1 {v16.8h, v17.8h, v18.8h, v19.8h}, [x0], #64
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add x1, x13, x19
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mov x2, x14
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L1:
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cmp x3, #0
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beq End
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mov x19, #16
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L1Loop:
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ld1 {v16.8h}, [x20] // assign bias
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mov x13, x1
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mov x14, x2
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mov x9, x6
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L1LoopH:
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mov x10, x5
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L1LoopW:
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ld1 {v8.8h}, [x2], #16
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ld1 {v0.8h}, [x1], #16
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subs x10, x10, #1
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fmla v16.8h, v8.8h, v0.8h
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bne L1LoopW
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subs x9, x9, #1
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add x1, x1, x8
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bne L1LoopH
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subs x3, x3, #1
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fmax v16.8h, v16.8h, v10.8h
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fmin v16.8h, v16.8h, v11.8h
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st1 {v16.8h}, [x0], #16
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add x1, x13, x4
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mov x2, x14
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bne L1Loop
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End:
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//mov x10, x23
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//mov x11, x24
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//mov x0, x21
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//mov x1, x22
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mov x3, x25
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subs x15, x15, #1
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add x0, x21, x24
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add x1, x22, x23
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bne LoopDY
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ldp x23, x24, [sp, #(16 * 8)]
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ldp x25, x26, [sp, #(16 * 7)]
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ldp x27, x28, [sp, #(16 * 6)]
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ldp x19, x20, [sp, #(16 * 5)]
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ldp x21, x22, [sp, #(16 * 4)]
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ldp d8, d9, [sp, #(16 * 3)]
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ldp d10, d11, [sp, #(16 * 2)]
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ldp d12, d13, [sp, #(16 * 1)]
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ldp d14, d15, [sp], #(16 * 9)
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ret
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#endif
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